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A B C D E




1 1




2



Compal confidential 2




EPW00 Schematics Document
Mobile AMD Athlon 64 with
3
ATI RS480M+ATI SB400 3




2005-04-15
REV:0.5



4 4




Security Classification Compal Secret Data
Issued Date 2005/03/11 Deciphered Date 2006/03/11 Title
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2541 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 15, 2005 Sheet 1 of 58
A B C D E
A B C D E




Compal confidential
File Name : LA-2541

Thermal Sensor
ADM1032 Memory BUS(DDR)
1
Mobile 1

page 4
AMD Athlon 64 DDR1 -333 DDR-SO-DIMM X2
BANK 0, 1, 2, 3 page 8,9,10
754-pin
Fan Control Single Channel Clock Generator
page 4
page 4, 5, 6, 7 ICS 951418
page 15


HT 16x16 1000MHZ
New Card
1 x PCIE Connectorpage 25

LVDS Panel ATI-RS480M
Interface page 16 USB conn X3
page 33
705 BGA
page 11, 12, 13, 14
2 CRT & TV OUT Finger print 2


page 17
page 33 RJ11 CONN
A-Link Express
page 30,39
2 x PCIE
BT Conn
page 33
USB2.0
MO DEM
ATI-SB400 AC-LINK Audio CKT page 30
page 29
3.3V 33 MHz PCI BUS 564 BGA ATA-100 Primary IDE
ATA-100 Secondary IDE HDD AMP & Audio Jack
IDSEL:AD18 IDSEL:AD17 IDSEL:AD20 page 18,19,20,21 page 31
(PIRQH#,GNT#1,REQ#1) (PIRQG#,GNT#3,REQ#3) (PIRQE#/F#,GNT#2,REQ#2) Connectorpage 34

Mini PCI LAN CardBus & 1394 CDROM
socket BCM5788M Controller TI 7611 Connectorpage SPR Conn.
LPC BUS 34 *RJ11 Conn
page 28 page 26 page 23,24
3
*RJ45 Conn 3
*Line IN Jack
*Line OUT Jack
RTC CKT. BIOS
page 18 RJ45 Slot 0 Card 13 94 EC SMSC SUPER I/O *PS/2x2
page 38 *Parallel Port
CONN page 24 reader CONN LPC47N250 LPC47N217 *Serial Port
page 27 page 23 page 23 page 37 page 36 *CRT
*TV-OUT
Power OK CKT. *PCI Express
page 40 *USB x2
Touch Pad Int.KBD
CONN page page 38
33
page 39
Power On/Off CKT.
page 38




4
DC/DC Interface CKT. 4

page 41




Power Circuit DC/DC Security Classification Compal Secret Data
Issued Date 2005/03/01 Deciphered Date 2006/03/11 Title
page 40~47 Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2541 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 15, 2005 Sheet 2 of 58
A B C D E
A




Voltage Rails Symbol note:
+5VS
+3VS :means digital ground.
power
plane +2.5VS
+5V
+1.8VS
+5VALW +2.5V :means analog ground.
+1.5VS
+3VALW +1.25V
+2.5VDDA
State +1.8VALW
+CPU_CORE @ :means reserved(un-mount).
+1.2V_HT
+RS480_Core
[email protected] :means populate for BCM4401 only.
S0 O O O
[email protected] :means populate for BCM5788M only.
S1
O O O
S3
O O [email protected] :means populate for PCI7611 only.
X
S5 S4/AC
O X X [email protected] :means populate for PCI4510 only.
S5 S4/AC don't exist
Only +3VL ON
X X
O MEANS ON
X MEANS OFF




PCI Devices

1
Jump Normal operation KBC Internal ROM flash Comment 1




INTERNAL PJ1 Short Pad Short Pad +3VL
PJ3 Short Pad Short Pad +3VALW
DEVICE PIRQ
PJ4 Short Pad Short Pad +1.8VALW
SMBUS PJ5 Short Pad Short Pad +5VALW
IDE A PJ6 Short Pad Short Pad +1.5VS
LPC I/F PJ7 Short Pad Short Pad +2.5V
PCI to PCI PJ8 Short Pad Short Pad +1.25V
AC97 AUDIO B PJ9 Short Pad Short Pad +1.2V_HT
AC97 MODEM B PJ11 Short Pad Short Pad
OHCI#1 USB D PJ12 Short Pad Short Pad
OHCI#1 USB D PJ14 Short Pad Short Pad +RS480_Core
EHCI USB D J1 Short Pad No Short Pad For ATE
SATA#1 A J2 Short Pad No Short Pad For ATE
SATA#2 A J3 No Short Pad No Short Pad
J4 No Short Pad No Short Pad Clear CMOS

EXTERNAL J5 No Short Pad Short Pad For ATE
IDSEL # REQ/GNT #
J6 No Short Pad Short Pad For ATE
CARD BUS & 1394 AD20 2 E, F J7 No Short Pad Short Pad For ATE
L AN AD17 3 H J8 Short Pad No Short Pad For ATE
Mini-PCI AD18 1 G J9 No Short Pad Short Pad For ATE




Security Classification Compal Secret Data
Issued Date 2005/03/01 Deciphered Date 2006/03/11 Title
Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2541 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 15, 2005 Sheet 3 of 58
A
A B C D E




H_CADIP[0..15] H_CADOP[0..15]
<11> H_CADIP[0..15] H_CADIN[0..15] H_CADON[0..15] H_CADOP[0..15] <11>
<11> H_CADIN[0..15] H_CADON[0..15] <11>


U10A

Claw Hammer-DTR
4 H_CADIP15 H_CADOP15 4
T25 N26
H_CADIN15
H_CADIP14
R25
U27
L0_CADIN_H15
L0_CADIN_L15
L0_CADOUT_H15
L0_CADOUT_L15 N27
L25
H_CADON15
H_CADOP14
PWM Fan Control circuit
H_CADIN14 L0_CADIN_H14 L0_CADOUT_H14 H_CADON14
U26 L0_CADIN_L14 L0_CADOUT_L14 M25
H_CADIP13 V25 L26 H_CADOP13
H_CADIN13 L0_CADIN_H13 L0_CADOUT_H13 H_CADON13
U25 L0_CADIN_L13 L0_CADOUT_L13 L27
H_CADIP12 H_CADOP12 +5VS
W27 L0_CADIN_H12 L0_CADOUT_H12 J25
H_CADIN12 W26 K25 H_CADON12
L0_CADIN_L12 L0_CADOUT_L12




HTT Interface
H_CADIP11 AA27 G25 H_CADOP11
H_CADIN11 L0_CADIN_H11 L0_CADOUT_H11 H_CADON11
AA26 L0_CADIN_L11 L0_CADOUT_L11 H25
H_CADIP10 AB25 G26 H_CADOP10 JP7
L0_CADIN_H10 L0_CADOUT_H10




1
H_CADIN10 AA25 G27 H_CADON10 1 1
H_CADIP9 L0_CADIN_L10 L0_CADOUT_L10 H_CADOP9 D21 C399 C400 1
AC27 L0_CADIN_H9 L0_CADOUT_H9 E25 2
H_CADIN9 AC26 F25 H_CADON9
H_CADIP8 L0_CADIN_L9 L0_CADOUT_L9 H_CADOP8 RB751V_SOD323 4.7U_0805_10V4Z 0.1U_0402_16V4Z ACES_85205-0200
AD25 L0_CADIN_H8 L0_CADOUT_H8 E26
H_CADIN8 H_CADON8 2 2
AC25 E27




2
H_CADIP7 L0_CADIN_L8 L0_CADOUT_L8 H_CADOP7
T27 L0_CADIN_H7 L0_CADOUT_H7 N29
H_CADIN7 T28 P29 H_CADON7
H_CADIP6 L0_CADIN_L7 L0_CADOUT_L7 H_CADOP6 +3VS FAN
V29 L0_CADIN_H6 L0_CADOUT_H6 M28
H_CADIN6 U29 M27 H_CADON6
H_CADIP5 L0_CADIN_L6 L0_CADOUT_L6 H_CADOP5
V27 L0_CADIN_H5 L0_CADOUT_H5 L29




1
2
5
6
H_CADIN5 V28 M29 H_CADON5
L0_CADIN_L5 L0_CADOUT_L5




5
H_CADIP4 Y29 K28 H_CADOP4 U28 D Q28
H_CADIN4 L0_CADIN_H4 L0_CADOUT_H4 H_CADON4 G
W29 K27 1




P
L0_CADIN_L4 L0_CADOUT_L4 <38> FAN_PWM INB
H_CADIP3 AB29 H28 H_CADOP3 4 3 SI3456DV-T1_TSOP6
H_CADIN3 L0_CADIN_H3 L0_CADOUT_H3 H_CADON3 THERM# O S
AA29 L0_CADIN_L3 L0_CADOUT_L3 H27 2 INA




G
H_CADIP2 AB27 G29 H_CADOP2




4
H_CADIN2 L0_CADIN_H2 L0_CADOUT_H2 H_CADON2 TC7SH00FU_SSOP5
AB28 H29




3
H_CADIP1 L0_CADIN_L2 L0_CADOUT_L2 H_CADOP1
AD29 L0_CADIN_H1 L0_CADOUT_H1 F28
H_CADIN1 AC29 F27 H_CADON1
H_CADIP0 L0_CADIN_L1 L0_CADOUT_L1 H_CADOP0
AD27 L0_CADIN_H0 L0_CADOUT_H0 E29
H_CADIN0 AD28 F29 H_CADON0
3 L0_CADIN_L0 L0_CADOUT_L0 3



H_CLKIP1 Y25 J26 H_CLKOP1
+1.2V_HT <11> H_CLKIP1 L0_CLKIN_H1 L0_CLKOUT_H1 H_CLKOP1 <11>
H_CLKIN1 W25 J27 H_CLKON1
<11> H_CLKIN1 L0_CLKIN_L1 L0_CLKOUT_L1 H_CLKON1 <11>
H_CLKIP0 Y27 J29 H_CLKOP0
<11> H_CLKIP0 L0_CLKIN_H0 L0_CLKOUT_H0 H_CLKOP0 <11>
H_CLKIN0 Y28 K29 H_CLKON0
<11> H_CLKIN0 L0_CLKIN_L0 L0_CLKOUT_L0 H_CLKON0 <11>
R353
1 2 49.9_0402_1% H_CTLIP1 R27 N25
R354 L0_CTLIN_H1 L0_CTLOUT_H1
1 2 49.9_0402_1% H_CTLIN1 R26 L0_CTLIN_L1 L0_CTLOUT_L1 P25
H_CTLIP0 T29 P28 H_CTLOP0
<11> H_CTLIP0 L0_CTLIN_H0 L0_CTLOUT_H0 H_CTLOP0 <11>
H_CTLIN0 R29 P27 H_CTLON0
<11> H_CTLIN0 L0_CTLIN_L0 L0_CTLOUT_L0 H_CTLON0 <11>
+1.2V_HT AF27 AJ27 LDTSTOP#
L0_REF1 LDTSTOP_L LDTSTOP# <13,18>
AE26 L0_REF0
R347 44.2_0603_1% 1 2 +2.5VS
2 1 LVREF1 FOX_PZ75403-2941-42 R336 1.2K_0402_5%
LVREF0
1




R350

44.2_0603_1%
2




2 2




Thermal Sensor
+3VS

W =15mil
ADM1032
2
C199
THERMDA_CPU
THERMDA_CPU <6>
0.1U_0402_16V4Z
1 THERMDC_CPU
THERMDC_CPU <6>
1




R124 U11
1 VDD SCLK 8 SB_SCLK <8,9,15,19>
10K_0402_5%
THERMDA_CPU 2 7 SB_SDAT <8,9,15,19>
2




C202 D+ SDATA
THERMDC_CPU 3 6 THERM_SCI#
D- ALERT# THERM_SCI# <19>
2200P_0402_50V7K
THERM# 4 5
THERM# GND

ADM1032AR_SOP8




1 1




Security Classification Compal Secret Data
Issued Date 2005/03/01 Deciphered Date 2006/03/11 Title
Claw Harmmer CPU (Host Bus)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2541 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 15, 2005 Sheet 4 of 58
A B C D E
A B C D E




+1.25VREF_CPU
+2.5V U10B
50 mil width AG12 MEMVREF1
DDR_CLK5/5# & DDR_CLK7/7#
34.8_0603_1% 2
34.8_0603_1% 2
1 R370 MEMZN D14
1 R369 MEMZP C14
MEMZN Claw Hammer-DTR route to nearest DIMM
MEMZP DDR_CLK4/4# & DDR_CLK6/6#
<8> DDR_SDQ[0..63]
DDR_SDQ63 A16 AE8 DDR_CKE0 route to farthest DIMM
MEMDATA63 MEMCKEA DDR_CKE0 <8>
DDR_SDQ62 B15 AE7 DDR_CKE1
MEMDATA62 MEMCKEB DDR_CKE1 <9>
DDR_SDQ61 A12
DDR_SDQ60 MEMDATA61 DDR_CLK7
1 B11 MEMDATA60 MEMCLK_H7 D10 DDR_CLK7 <8> 1
DDR_SDQ59 A17 C10 DDR_CLK7#
MEMDATA59 MEMCLK_L7 DDR_CLK7# <8>
DDR_SDQ58 A15 E12 DDR_CLK6
MEMDATA58 MEMCLK_H6 DDR_CLK6 <9>
DDR_SDQ57 C13 E11 DDR_CLK6#
MEMDATA57 MEMCLK_L6 DDR_CLK6# <9>
DDR_SDQ56 A11 AF8 DDR_CLK5 DDR_CLK7 R130 1 2 120_0402_5% DDR_CLK7#
MEMDATA56 MEMCLK_H5 DDR_CLK5 <8>
DDR_SDQ55 A10 AG8 DDR_CLK5# DDR_CLK6 R129 1 2 120_0402_5% DDR_CLK6#
MEMDATA55 MEMCLK_L5 DDR_CLK5# <8>
DDR_SDQ54 B9 AF10 DDR_CLK4 DDR_CLK5 R92 1 2 120_0402_5% DDR_CLK5#
MEMDATA54 MEMCLK_H4 DDR_CLK4 <9>
DDR_SDQ53 C7 AE10 DDR_CLK4# DDR_CLK4 R83 1 2 120_0402_5% DDR_CLK4#
MEMDATA53 MEMCLK_L4 DDR_CLK4# <9>
DDR_SDQ52 A6 V3
DDR_SDQ51 MEMDATA52 MEMCLK_H3 within 1 .00"
C11 MEMDATA51 MEMCLK_L3 V4
DDR_SDQ50 A9 K5
DDR_SDQ49 MEMDATA50 MEMCLK_H2
A5 MEMDATA49 MEMCLK_L2 K4
DDR_SDQ48 B5 R5
DDR_SDQ47 MEMDATA48 MEMCLK_H1
C5 MEMDATA47 MEMCLK_L1 P5
DDR_SDQ46 A4 P3
DDR_SDQ45 MEMDATA46 MEMCLK_H0
E2 MEMDATA45 MEMCLK_L0 P4
DDR_SDQ44 E1
DDR_SDQ43 MEMDATA44
A3 MEMDATA43 MEMCS_L7 D8
DDR_SDQ42 B3 C8
DDR_SDQ41 MEMDATA42 MEMCS_L6
E3 MEMDATA41 MEMCS_L5 E8
DDR_SDQ40 F1 E7
DDR_SDQ39 MEMDATA40 MEMCS_L4 DDR_SCS#3
G2 MEMDATA39 MEMCS_L3 D6 DDR_SCS#3 <9>
DDR_SDQ38 G1 E6 DDR_SCS#2
MEMDATA38 MEMCS_L2 DDR_SCS#2 <9>
DDR_SDQ37 DDR_SCS#1




DDR Memory
L3 MEMDATA37 MEMCS_L1 C4 DDR_SCS#1 <8>
DDR_SDQ36 L1 E5 DDR_SCS#0
MEMDATA36 MEMCS_L0 DDR_SCS#0 <8>
DDR_SDQ35 G3
DDR_SDQ34 MEMDATA35
J2 MEMDATA34 MEMRASA_L H5 DDR_SRASA# <8>
DDR_SDQ33 L2 D4
MEMDATA33 MEMCASA_L DDR_SCASA# <8>
DDR_SDQ32 M1 G5 +2.5V
MEMDATA32 MEMWEA_L DDR_SWEA# <8>




A CHANGEL ADDRESS
2 DDR_SDQ31 W1 2
DDR_SDQ30 MEMDATA31
W3 MEMDATA30 MEMBANKA1 K3 DDR_SBSA1 <8>




1
DDR_SDQ29 AC1