Text preview for : fujitsu_siemens_amilo_li3710_li3910_quanta_ef7_rev_1a_sch.pdf part of Fujitsu fujitsu siemens amilo li3710 li3910 quanta ef7 rev 1a sch Fujitsu fujitsu_siemens_amilo_li3710_li3910_quanta_ef7_rev_1a_sch.pdf
Back to : fujitsu_siemens_amilo_li3 | Home
1 2 3 4 5 6 7 8
PCB STACK UP
LAYER 1 : TOP
Li 37/39 http://hobi-elektronika.net
Block Diagram 01
LAYER 2 : SGND1 CPU CPU THERMAL 14.318MHz
Penryn SENSOR
LAYER 3 : IN1 CPU CORE ISL6266A
A A
LAYER 4 : IN2 478P (uPGA)/35W CLK_CPU_BCLK,CLK_CPU_BCLK# CLOCK GEN
LAYER 5 : VCC CLK_MCH_BCLK,CLK_MCH_BCLK# ALPRS365B MLF64PIN
DREFCLK,DREFCLK#
LAYER 6 : BOT DREFSSCLK,DREFSSCLK#
VCCP +1.5V AND GMCH
1.05V(RT8204)
NORTH BRIDGE
DDRII 667 MHz
DDRII-SODIMM1 CRT
DDRII SMDDR_VTERM Cantiga
1.8V/1.8VSUS(RT8202) LCD CONN
DDRII 667MHz GL40
B
DDRII-SODIMM2 B
32.768KHz NBSRCCLK, NBSRCCLK#
DMI LINK
USB2.0
SATA - HDD
SATA0 150MB
USB2.0 Ports Webcam Mini PCI-E x1
Express
SATA1 150MB SOUTH BRIDGE Card
SATA - CD - ROM X3
ICH-9M
PCI-E
PCIE X 6
C USB X 12 Azalia C
Mini PCI-E LAN Express Card Realtek 24.576MHz
Card X 1 Realtek RTS5158E
power switch
10/100
Codec RICOH
RTL8102EL R5538D
SYSTEM POWER MAX17101 Realtek
32.768KHz LPC (NewCard)
ALC662-GR
Keyboard 25MHz
RJ45 Memory
KBC CardReader
Touch Pad Audio
ITE 8502E-J Amplifier
TPA6017A2
SYSTEM CHARGER Headphone
MAX17005
LINE Out SPDIF
D D
LINE IN
Speaker
FAN SPI ROM
8Mbits PROJECT :EF7
MIC
Quanta Computer Inc.
Size Document Number Rev
Custom Block Diagram 1A
Date: Friday, June 13, 2008 Sheet 1 of 34
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
http://hobi-elektronika.net
+3V
L13
HCB1608KF-181T15_1.5A
+CK_VDD_MAIN
[4,6,9,10,11,12,13,14,15,16,17,18,19,22,23,24,25,26,27,28,29,30,31,32]
[3,4,5,6,8,9,12,15,27,30,32]
+3V
+1.05V
02
C222 C244 C223 C247 C212 C210 U9
10U/6.3V/X5_8 .1U/10V/X5_4 .1U/10V/X5_4
.1U/10V/X5_4
.1U/10V/X5_4
.1U/10V/X5_4
+CK_VDD_MAIN 16 54
VDDPLL3 CPUCLKT0 CLK_CPU_BCLK [3]
9 VDD48 CPUCLKC0 53 CLK_CPU_BCLK# [3]
2
61
VDDPCI
VDDREF
CK505 CPUCLKT1 51 CLK_MCH_BCLK [5]
A L16 VDDCPU 39 50 A
VDDSRC CPUCLKC1 CLK_MCH_BCLK# [5]
HCB1608KF-181T15_1.5A VDDCPU 55 VDDCPU CPU_ITP
CPUT2_ITP/SRCT8 47 T67
C260 C240 +CK_VDD_MAIN2 12 46 CPU_ITP#
10U/6.3V/X5_8 .1U/10V/X5_4 VDD96I/O CPUT2_ITP/SRCC8 T68
20 VDDPLL3I/O
26 VDDSRCI/O DOTT_96/SRCT0 13 DREFCLK [6]
45 VDDSRCI/O DOTC_96/SRCC0 14 DREFCLK# [6]
36 VDDSRCI/O
27MHz_Nonss/SRCCLK1/SE1 17 DREFSSCLK [6]
L17 +CK_VDD_MAIN2 49 18
VDDCPU_IO 27Mhz_ss/SRCCLC1/SE2 DREFSSCLK# [6]
HCB1608KF-181T15_1.5A 48 NC
SRCCLKT2/SATACL 21 CLK_PCIE_SATA [12]
SRCCLKC2/SATACL 22 CLK_PCIE_SATA# [12]
C261 C249 C239 C248 C209 C208 C211 CG_XIN 60
10U/6.3V/X5_8 .1U/10V/X5_4 CG_XOUT X1 R_CLK_PCIE_VGA
59 X2 SRCCLKT3/CR#_C 24 T37
.1U/10V/X5_4
.1U/10V/X5_4
.1U/10V/X5_4
.1U/10V/X5_4
.1U/10V/X5_4
25 R_CLK_PCIE_VGA#
SRCCLKC3/CR#_D T38
SRCCLKT4 27 CLK_PCIE_3GPLL [6] 0513 SWAP
SRCCLKC4 28 CLK_PCIE_3GPLL# [6] CLK_PCIE_3GPLL vs CLK_PCIE_LAN
[14] CK_PWG 56 CK_PWRGD/PD# PCI_STOP# 38 PM_STPPCI# [14]
CLK_PCIE_MINI vs CLK_PCIE_ICH
CPU_BSEL1 FSB 57 37
FSLB/TEST_MODE CPU_STOP# PM_STPCPU# [14]
R176 2.2K_4
Y2 XTAL_14.318MH 41
SRCCLKT6 CLK_PCIE_MINI [23]
SRCCLKC6 40 CLK_PCIE_MINI# [23]
CG_XIN 1 2 CG_XOUT
[10,11,23] CGCLK_SMB CGCLK_SMB R174 0_4 64 44
SCLK SRCCLKT7/CR#_F CLK_PCIE_ICH [13]
[10,11,23] CGDAT_SMB CGDAT_SMB 63 43
SDATA SRCCLKC7/CR#_E CLK_PCIE_ICH# [13]
C265 C264 for EMI
SRCCLKT9 30 CLK_PCIE_LAN [18]
B 27P/50V/NPO_4 27P/50V/NPO_4 15 31 B
GND SRCCLKC9 CLK_PCIE_LAN# [18]
19 GND
C234 11 34 R_CLK_PCIE_NEW_C 2 1 0X2
GND48 SRCCLKT10 CLK_PCIE_NEW_C [23]
*27P/50V 52 35 R_CLK_PCIE_NEW_C# 4 3 RP29
GNDCPU SRCCLKC10 CLK_PCIE_NEW_C# [23]
8 GNDPCI
+3V for EMI 58 33 NEW-CARD_CLK_REQ#_R R167 475/F_4 NEW-CARD_CLK_REQ#
GNDREF SRCCLKT11/CR#_H R149 NEW-CARD_CLK_REQ# [23]
23 32 CLK_3GPLLREQ#_R 475/F_4 CLK_MCH_OE#
GNDSRC SRCCLKC11/CR#_G CLK_MCH_OE# [6]
29 GNDSRC
42 GNDSRC
1 PCI_ICH
R165 R158 PCICLK0/CR#_A PCIE_LANREQ#_R T48 R132 475/F_4 PCIE_LANREQ#
PCICLK1/CR#_B 3 PCIE_LANREQ# [18]
10K_4 10K_4 4 PCLK_2
PCICLK2/TME T39 R123
2
5 PCLK_MINI_LPC 33_4 PCLK_LPC_DEBUG
PCICLK3 PCLK_LPC_DEBUG [23]
6 FCTSEL1 R122 33_4 PCLK_LPC_8512
PCICLK4/27_SELECT PCLK_LPC_8512 [24]
3 1 CGDAT_SMB
[14] PDAT_SMB
ITP_EN R120 33_4 PCLK_ICH
PCLK_ICH [13]
Q8
2N7002 7 R125 22_4 CLK_48M_USB_CR
PCI_F5/ITP_EN CLK_48M_USB_CR [21]
R119 22_4 CLK_48M_USB
CLK_48M_USB [14]
+3V 10 FSA R126 2.2K_4 CPU_BSEL0
USB_48MHZ/FSLA
62 R178 22_4 CLK_14M_ICH
FSLC/TST_SL/REF CLK_14M_ICH [14]
2
ICS9LPRS365BGLFT FSC R177 10K_4 CPU_BSEL2
3 1 CGCLK_SMB
[14] PCLK_SMB
Q7
2N7002
GCLK_SEL = FCTSEL1
C C
+3V +3V ITP_EN +3V
FCTSEL1 PIN13 PIN14 PIN17 PIN18
(PIN13)
R135 0=UMA DOT96T DOT96C SRCT1/LCDT_100 SRCT1/LCDT_100 CLK_MCH_OE# R152 10K_4
R129 R121 10K_4
10K_4 *10K_4 NEW-CARD_CLK_REQ# R160 10K_4
Disable ITP 1 = External
SRCT0 SRCC0 27Mout-NSS 27Mout-SS PCIE_LANREQ# R133 10K_4
FCTSEL1 VGA
PCLK_2
R136 2 1 0
10K_4
R130 FSC FSB FSA CPU SRC PCI 0428 delete SIO connection
*4.7K_4 CPU Clock select
1 0 1 100 100 33
PCI4/27_Select: CPU_BSEL0 R117 0_4 0 0 1 133 100 33 C205 27P/50V/NPO_4 CLK_48M_USB_CR
[3] CPU_BSEL0 MCH_BSEL0 [6]
1=27MHz,0=SRC_100MHz C202 27P/50V/NPO_4 CLK_48M_USB
of Pin17 & Pin18.
0 1 1 166 100 33
R118 *1K_4 0 1 0 200 100 33 C245 27P/50V/NPO_4 CLK_14M_ICH
0=overclocking 0512 Change Strap CPU_BSEL1 R186 0_4 0 0 0 266 100 33 C524 27P/50V/NPO_4 PCLK_LPC_DEBUG
[3] CPU_BSEL1 MCH_BSEL1 [6]
of CPU and 1 0 0 333 100 33 C204 27P/50V/NPO_4 PCLK_LPC_8512
SRC Allowed
+1.05V R185 *1K_4 1 1 0 400 100 33 C203 27P/50V/NPO_4 PCLK_ICH
D D
1 = overclocking CPU_BSEL2 R189 0_4 1 1 1 RSVD 100 33 for EMI
[3] CPU_BSEL2 MCH_BSEL2 [6]
of CPU and SRC
not Allowed
+1.05V R183 *1K_4
PROJECT :EF7
0428 correct Net name PCLK_2
0519 Update BSEL default follwed CPU. Quanta Computer Inc.
Size Document Number Rev
Custom CLOCK GENERATOR 1A
Date: Wednesday, July 02, 2008 Sheet 2 of 34
1 2 3 4 5 6 7 8
5 4 3 2 1
http://hobi-elektronika.net [2,4,5,6,8,9,12,15,27,30,32] +1.05V
[5] H_A#[35:3]
H_A#3
H_A#4
J4
U17A
A[3]# ADS# H1
T30
H_ADS# [5]
[5] H_D#[63:0]
H_D#0
H_D#1
E22
U17B
D[0]# D[32]# Y22 H_D#32
H_D#33
H_D#[63:0]
03
L5 A[4]# BNR# E2 H_BNR# [5] F24 D[1]# D[33]# AB24
ADDR GROUP 0
ADDR GROUP 0
H_A#5 L4 G5 H_D#2 E26 V24 H_D#34
A[5]# BPRI# H_BPRI# [5] D[2]# D[34]#
H_A#6 K5 H_D#3 G22 V26 H_D#35
H_A#7 A[6]# H_D#4 D[3]# D[35]# H_D#36
M3 A[7]# DEFER# H5 H_DEFER# [5] F23 D[4]# D[36]# V23
H_A#8 N2 F21 H_D#5 G25 T22 H_D#37
A[8]# DRDY# H_DRDY# [5] D[5]# D[37]#
H_A#9 J1 E1 H_D#6 E25 U25 H_D#38
A[9]# DBSY# H_DBSY# [5] D[6]# D[38]#
DATA GRP 0
DATA GRP 0
DATA GRP 2
D H_A#10 N3 H_D#7 E23 U23 H_D#39 D
H_A#11 A[10]# H_D#8 D[7]# D[39]# H_D#40
P5 A[11]# BR0# F1 HBREQ#0 [5] K24 D[8]# D[40]# Y25
H_A#12 P2 H_D#9 G24 W22 H_D#41
A[12]# D[9]# D[41]#
CONTROL
H_A#13 L2 D20 H_IERR# R11 56.2/F_4 +1.05V H_D#10 J24 Y23 H_D#42
H_A#14 A[13]# IERR# H_D#11 D[10]# D[42]# H_D#43
P4 A[14]# INIT# B3 H_INIT# [12] J23 D[11]# D[43]# W24
H_A#15 P1 H_D#12 H22 W25 H_D#44
H_A#16 A[15]# H_D#13 D[12]# D[44]# H_D#45
R1 A[16]# LOCK# H4 H_LOCK# [5] F26 D[13]# D[45]# AA23
M1 H_D#14 K22 AA24 H_D#46
[5] H_ADSTB#0 ADSTB[0]# H_CPURST# [5] D[14]# D[46]#
C1 H_D#15 H23 AB25