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A B C D E
ASUS CONFIDENTIAL
MODEL NAME : Elsa
1
PCB NO : ??? 1
ASUS P/N : ???
2 2
Lanai UMA Schematics Document
uFCPGA Mobile Merom
Intel Crestline-GM + ICH8M
3 3
2007-03-19
REV :1.2(DELL: X02)
4 4
5 MB PCB 5
Part Number Description
BOM NO. ???
DA800004H0L PCB 00B LA-3071P REV0 M/B
PCB P/N: ???
REVISION DATE: Monday, March 19, 2007 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: 1.2 SHEET 1 OF 68 Cover Page RELEASE DATE :
A B C D E
5 4 3 2 1
LANAI: UMA CLOCK
CK410M+LP
POWER POWER SEQUENCE PG 51 PG 21
LOGIC
D POWER POWER PG 57 Merom POWER D
CON. CHARGER POWER VCORE PG 53
XDP (478 Micro-FCPGA)
PG 59 POWER CONTROL PG 49 PG 52
POWER I/O PG 55
SWITCH PG 7,8
POWER SYSTEM
+1.5V_RUN/+1.05V_VCCP
PG 54
5V_ALW & 3.3V_ALW
DISCHARGE PATH PG 49 (Symbol Rev.09) REGULATOR PG 58
PG 56
+3.3V_SUS/+5V_SUS/+3.3V_RUN REGULATOR
+5V/+3.3V/+1.8V/+1.25_RUN +VCC_GFX_CORE/+1.25V_RUN +1.8V_SUS/+0.9V_DDR_VTT
Panel Connector LVDS 533/667 MHZ DDR II
PG 28 DDR2-SODIMM1
Crestline PG 19
1299 uFCBGA
PG 9,10,11,12,13,14 533/667 MHZ DDR II DDR2-SODIMM2
C
(Symbol Rev.09) PG 19 C
IO Board
CRT CONN. VGA VGA
USB2.0(P0,P1) USB CONN.
TVOUT DMI INTERFACE
TVOUT PG 39
TV CONN.
USB Board
USB2.0(P2,3) D.B
USB CONN.x2 CON PCIE (Lane6)
USB2.0(P2,3)
PCIEx1 (Lane2) PCIEx1 (Lane2) PCI
MINI-CARD
WLAN PG 50 ICH8-M
USB2.0(P9) PCIE (Lane4)
676 BGA
MINI-CARD USB2.0(P9)
WWAN PG 15,16,17,18 USB2.0(P6)
CARD READER
USB2.0(P7) 1394/R5C833 BCM5906KMLG
(Symbol Rev.09) PG 32,33,34 QFN-68 PG 47
IHDA
B
SIM USB2.0(P5) B
CARD CAMERA
PG 28
EXPRESS-CARD RJ45/Magnetic
SIM CARD Board R5538 PG 48
PG 35
SPI LPC SATA SATA-HDD
AUDIO/AMP MDC PG 31
PG 44,45,46 PG 36
IDE CD-ROM
PG 31
SIO SIO
S/PDIF DIGITAL Speaker WtoB MEC5025 ECE5011
TO TV MIC. CON CON 128KB Flash Expander
CONN. TMKBC BC USB 2.0 Hub(4) Bluetooth
PG 30 PG 46 PG 46 PG 41
PG 28 128 Pins VTQFP 128 Pins VTQFP
PG 37 PG 38
A
Audio RJ11 SPI PS/2
A
Jacks
*3 Touchpad FAN &THERMAL USER SNIFFER CAPBTN
CIR FLASH CON. EMC4001 INTERFACE CON.
PG 41 PG 40 PG 41 PG 43 PG 42 PG 42 PG 40
JACK Board RJ11 Board
REVISION DATE: Monday, March 19, 2007 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: 1.2 SHEET 2 OF 68 BLOCK DIAGRAM RELEASE DATE :
5 4 3 2 1
A B C D E
INDEX
Pg# Description DNI LIST Pg# Description DNI LIST
01 Cover Page 63 POWER CIRCUIT CHANGE LIST
1 1
02 Schematic Block Diagram 64 Modem board cover page
03 INDEX 65 RJ-11 CONN
04 Bus connection 66 Modem board change List
05 SMBUS BLOCK 67 USB board cover page
06 Power Rail 68 USB PORT ( SINGLE * 2 )
07-08 CPU ( Merom Penryn )
09-14 Crestline
15-18 ICH8M
2 19-20 DDRII SO-DIMM( 533MHz 667MHz ) 2
21 Clock Generator ( CK410M+LP )
22-27 BLANK PAGE
28 LVDS CON & Camera & DMIC
29 RGB CON
30 TV OUT CON
31 SATA(HDD & CD_ROM)
32-34 MEDIA CARD READER / 1394 ( R5C833 )
35 PCI-Express Card
3 3
36 MDC CONN
37 EC ( MEC5025 )
38 SIO ( ECE5011 )
39 USB PORT x 2
40 FLASH & RTC & CAPBTN CONN
41 TOUCH PAD & BT & CIR & LID
42 SWITCH & LED
43 HARDWARE MONITOR ( EMC4001 )
4 44-46 AUDIO CODEC & AMP 4
47 LOM BCM5906
48 Magnetics and RJ-45
49 Power Control Switch
50 BtoB CON
51 Power Sequence Logic
52 XDP
53-59 Power Circuit
60 SCREW PAD
5 5
61 Change List 1
62 Change List 2
REVISION DATE: Monday, March 19, 2007 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: Lanai 1.2 SHEET 3 OF 68 INDEX RELEASE DATE :
A B C D E
A B C D E
Footprint Definition PCI TABLE
PCI
Resistor Footprint is 0402 if there is no description DEVICE IDSEL REQ#/GNT# PIRQ
Capacitor Footprint is 0402 if there is no description PCI_REQ1# PCI_PIRQC#
1 R5C833 PCI_AD17 PCI_GNT1# 1
PCI_PIRQD#
Ferrite Bead Footprint is 0603 if there is no description
Layout Note
For all of ESD diode, they should be placed as close as
possible to connectors and the signals from connectors PCI Express TABLE
should be routed to ESD diodes first. There is no branch
or via before diodes Lane 1 WWAN / Mini Card
Lane 2 WLAN / Mini Card
2 Lane 3 2
Lane 4 ExpressCard
Lane 5
Lane 6 LAN BCM5906KMLG
USB TABLE
3 ICH8-0 User1 3
(EHCI#1) (Single port , in USB BD)
ICH8-1 User2
(EHCI#1) (Single port , in USB BD)
ICH8-2 User3
(EHCI#1) (Dual port-bottom , in I/O BD)
ICH8-3 User4
(EHCI#1) (Dual port-top , in I/O BD)
ICH8-4
(EHCI#1)
4 4
ICH8-5 Camera
(EHCI#1)
ICH8-6
(EHCI#2) ExpressCard
ICH8-7
(EHCI#2) BT Module
ICH8-8
(EHCI#2)
ICH8-9 WWAN / Mini Card
5 5
(EHCI#2)
Note : No USB for WLAN
REVISION DATE: Monday, March 19, 2007 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: Lanai 1.2 SHEET 4 OF 68 Bus Connection RELEASE DATE :
A B C D E
5 4 3 2 1
+3.3V_SUS +3.3V_SUS +3.3V_RUN
MEM_SCLK 197
2.2K 2.2K 2.2K 2.2K MEM_SDATA 195 DIMM 0
10K 10K
+3.3V_RUN
ICH8-M AJ26 ICH_SMBCLK
7002 MEM_SCLK 197
AD19 ICH_SMBDATA MEM_SDATA 195 DIMM 1
D
7002 D
AC17 AMT_SMBCLK
I/O Board
AE19 AMT_SMBDAT
+5V_MEDIA
7 30 30
8.2K 8.2K
8 Express Card 32 WWAN 32 WLAN
6 DOCK_SMBCLK
5 DOCK_SMBDAT CAPBTN Board
+3.3V_ALW +3.3V_RUN
2.2K 2.2K 2.2K 2.2K
C C
+3.3V_RUN
13 CKG_SMBCLK CLK_SCLK 16
7002
12 CKG_SMBDAT CLK_SDATA 17 CLK GEN.
+3.3V_ALW 7002
4.7K 4.7K
100 THRM_SMBCLK 12
99 THRM_SMBDAT +3.3V_ALW 11 ECE4001
SIO +3.3V_ALW
10
2.2K 2.2K 9 CHARGER
B
MEC5025 112 PBAT_SMBCLK
100
SMB_CLK 3
B
+3.3V_ALW Battery
111 PBAT_SMBDAT SMB_DAT 4 CONN.
100
+3.3V_ALW
8.2K 8.2K
8 LCD_SMBCLK 34
7 LCD_SMDDAT +3.3V_ALW 35
+3.3V_RUN 47pF 47pF
LVDS
Connector
2.2K 2.2K
A A
LCD_DDCCLK 43
VGA LCD_DDCDAT +3.3V_RUN 44
REVISION DATE: Monday, March 19, 2007 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: Lanai 1.2 SHEET 5 OF 68 SMBUS BLOCK RELEASE DATE :
5 4 3 2 1
A B C D E
ADAPTER
1 1
+RTC_CELL
+PWR_SRC
BATTERY
2 2
TPS51120 ISL6260C SN0508073 SN0508073
ISL6208
THERM_STP#
THERM_STP#
THERM_STP#
RUNPWROK
IMVP_VR_ON
1.25V_RUN_ON
1.5V_RUN_ON
1.05_RUN_ON
ALWON
ALWON
ALWON
DDR_ON
3 3
+5V_ +3.3V_RTC
ALW2 _LDO +5V_ALW +3.3V_ALW +VCC_CORE +1.5V_RUN +1.05V_VCCP +1.8V_SUS +1.25V_RUN
0.9V_DDR_VTT_ON
3.3V_SUS_ON
3.3V_RUN_ON
RUN_ON
SUS_ON
SI4800BDY BAT54S SI4800BDY FDS6612A SI4800BDY
DDR_ON
1.8V_RUN_ON
+5V_RUN +15V_ALW +5V_SUS +3.3V_RUN +3.3V_SUS TPS51100 FDS6612A
4 4
+0.9V_DDR_VTT +1.8V_RUN
EMC4001
EE
SIDE
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
5
+2.5V_RUN TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, 5
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
REVISION DATE: Monday, March 19, 2007 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: Lanai 1.2 SHEET 6 OF 68 Power Rail RELEASE DATE :
A B C D E
5 4 3 2 1
U25A U25B
H_A#[3..16] MOLEX/47387-4781 H_D#[0..63] MOLEX/47387-4781 H_D#[0..63]
9 H_A#[3..16] 9 H_D#[0..63] H_D#[0..63] 9
H_A#3 J4 H1 H_D#0 E22 Y22 H_D#32
A3# ADS# H_ADS# 9 D0# D32#
0
ADDR GROUP
H_A#4 L5 E2 H_D#1 F24 AB24 H_D#33
A4# BNR# H_BNR# 9 D1# D33#
H_A#5 L4 G5 H_D#2 E26 V24 H_D#34
A5# BPRI# H_BPRI# 9 D2# D34#
H_A#6 K5 H_D#3 G22 V26 H_D#35
A6# D3# D35#
DATA GRP 0
H_A#7 M3 H5 H_D#4 F23 V23 H_D#36
A7# DEFER# H_DEFER# 9 D4# D36#
H_A#8 N2 F21 H_D#5 G25 T22 H_D#37
A8# DRDY# H_DRDY# 9 D5# D37#
H_A#9 J1 E1 H_D#6 E25 U25 H_D#38
H_A#10 A9# DBSY# H_DBSY# 9 D6# D38#
N3 H_D#7 E23 U23 H_D#39
A10# H_BR0# 9 D7# D39#
H_A#11 P5 F1 H_D#8 K24 Y25 H_D#40
H_A#12 A11# BR0# H_D#9 D8# D40# H_D#41
DATA GRP 2
P2 A12# G24 D9# D41# W22
CONTROL
H_A#13 L2 D20 H_IERR# 1 2 H_D#10 J24 Y23 H_D#42
A13# IERR# +1.05V_VCCP D10# D42#
H_A#14 P4 B3 R159 56Ohm 5% H_D#11 J23 W24 H_D#43
H_A#15 A14# INIT# H_INIT# 15 D11# D43#
P1 H_D#12 H22 W25 H_D#44
D H_A#16 A15# H_D#13 D12# D44# H_D#45 D
R1 A16# LOCK# H4 H_LOCK# 9 F26 D13# D45# AA23
M1 H_D#14 K22 AA24 H_D#46
9 H_ADSTB#0 H_REQ#[0..4] ADSTB0# H_RESET# H_D#15 D14# D46# H_D#47
9 H_REQ#[0..4] RESET# C1 H_RESET# 9,52 H23 D15# D47# AB25
H_REQ#0 K3 F3 J26 Y26
H_REQ#1 REQ0# RS0# H_RS#0 9 9 H_DSTBN#0 DSTBN0# DSTBN2# H_DSTBN#2 9
H2 REQ1# RS1# F4 H_RS#1 9 9 H_DSTBP#0 H26 DSTBP0# DSTBP2# AA26 H_DSTBP#2 9
H_REQ#2 K2 G3 H25 U22
H_REQ#3 REQ2# RS2# H_RS#2 9 9 H_DINV#0 DINV0# DINV2# H_DINV#2 9
J3 REQ3# TRDY# G2 H_TRDY# 9
H_REQ#4 L1 H_D#[0..63] H_D#[0..63]
H_A#[17..35] REQ4# 9 H_D#[0..63] H_D#[0..63] 9
G6 H_D#16 N22 AE24 H_D#48
9 H_A#[17..35] HIT# H_HIT# 9 D16# D48#
H_A#17 Y2 E4 H_D#17 K25 AD24 H_D#49
A17# HITM# H_HITM# 9 D17# D49#
H_A#18 U5 H_D#18 P26 AA21 H_D#50
H_A#19 A18# XDP_BPM#0 Layout note: H_D#19 D18# D50# H_D#51
R3 A19# BPM0# AD4 XDP_BPM#0 52 R23 D19# D51# AB22
1
ADDR GROUP
H_A#20 W6 AD3 XDP_BPM#1 H_D#20 L23 AB21 H_D#52
A20# BPM1# XDP_BPM#1 52 Place voltage D20# D52#
DATA GRP 1
H_A#21 U4 AD1 XDP_BPM#2 H_D#21 M24 AC26 H_D#53
A21# BPM2# XDP_BPM#3 XDP_BPM#2 52 divider within D21# D53#
H_A#22 Y5 AC4 H_D#22 L22 AD20 H_D#54
XDP/ITP SIGNALS
A22# BPM3# XDP_BPM#4 XDP_BPM#3 52 D22# D54#
H_A#23 U1 AC2 0.5" of GTLREF H_D#23 M23 AE22 H_D#55
A23# PRDY# XDP_BPM#5 XDP_BPM#4 52 D23# D55#
H_A#24 R4 AC1 H_D#24 P25 AF23 H_D#56
A24# PREQ# XDP_TCK XDP_BPM#5 52 pin D24# D56#
H_A#25 T5 AC5 H_D#25 P23 AC25 H_D#57
A25# TCK XDP_TDI XDP_TCK 52 D25# D57#
H_A#26 T3 AA6