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Last Schematic Update Date:
06/01/2001
D
Cover Sheet 1 D
MS-6506 Version 0A
Block Diagram
GPIO Spec.
2
3
INTEL (R) Brookdale Chipset
Clock ICS950208 & ATA100 IDE CONNECTORS 4
Willamette/Northwood 478pin mPGA-B Processor Schematics
mPGA478-B INTEL CPU Sockets 5-6
FormFactor : Flex-ATX (22.4 X 19.2mm) for NEC-CI INTEL Brookdale MCH -- North Bridge 7-8
CPU: INTEL ICH2 -- South Bridge 9 - 10
Willamette/Northwood mPGA-478B Processor LPC Super I/O Winbond W83627HF 11
AC'97 Codec & Audio Amp TL072 & GAME 12
System Brookdale Chipset:
FWH -- BIOS & CNR RISER 13
C
INTEL MCH (North Bridge) + C
SDR DIMM-168PIN DIMM1,2 14
INTEL ICH2 (South Bridge)
On Board Chipset: AGP 4X SLOT (1.5V) 15
BIOS -- FWH PCI SLOT 1 & 2 16
LPC Super I/O -- W83627HF Front Panel & Connectors 17
Clock Generation -- ICS950208 USB & FAN Connectors 18
Votlage Regulator 19
Expansion Slots:
HIP6301V CPU Power ( PWM )-VRM9.0 20
AGP2.0 SLOT * 1
PCI2.2 SLOT * 2 IO Connectors 21
CNR SLOT * 1 Packing 22
B
Jumper Setting 23 B
Layout Guide 24-30
Power Delivery 31
History I 32
ERP BOM Function Description
601-6506-A10 MS-6506 Ver:0A With AGP,CNR,STR.
NEC-CI Led.
A A
M i c r o S t a r R e s tricted Secret
Title Rev
Cover Sheet
Document Number 0A
MS-6506
MICRO-STAR INT'L CO.,LTD. Last Revision Date:
Monday, June 04, 2001
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan Sheet
http://www.msi.com.tw 1 of 32
8 7 6 5 4 3 2 1
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D D
Page.17 Page.20 Page.5,6 (478PINS) Page.4
(100MHz)
Power
Supply VRM Willamette/Northwood CK408 Clock
9.2 Socket (mPGA478-B) (100MHz)
CONN
Scalable Bus
Scalable Bus/2
Page.15 4X (66MHz) AGP Page.7,8
AGP
4X(1.5V) AGP 4X MCH: Memory
AGP CONN (1.5V)
Controller HUB Page.14
(593PINS/FCBGA) (133MHz)
DIMM 1:2
( 66MHz X 4 ) HUB Interface
Page.18 Page.9,10 (14.318MHz)
C Heceta Hardware SM Bus Page.16 C
Monitor PCI (33MHz)
ICH2: I/O
(360PINS/EBGA)
PCI Slots 1:2
Page.4
Controller HUB
IDE CONN 1&2
(48MHz)
(33MHz)
(33MHz)
Page.18 Page.13
LPC Bus AC Link
USB Port 0:3 CNR Riser
(Shared slot)
Page.12
Page.13
Page.11
AC '97 Audio
FWH: Firmware HUB AMP
Codec
SIO Line Out
W83627HF
Telephone In
Page.19 MIC In
B Audio In B
Line In
PS2 Mouse & Parallel (1) Floppy Disk
Keyboard Serial (2) Drive CONN CD-ROM
A A
Micro Star Restricted Secret
Title Rev
Block Diagram
Document Number 0A
MS-6506
MICRO-STAR INT'L CO.,LTD. Last Revision Date:
Monday, June 04, 2001
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan Sheet
http://www.msi.com.tw 2 of 32
8 7 6 5 4 3 2 1
5 4 3 2 1
General Purpose I/O Spec.
D D
ICH2
GPIO Pin Type Function
GPIO 0 I REQ#A
GPIO 1 I PREQ#5
GPIO 2 I INTE#
GPIO 3 I INTF#
GPIO 4 I INTG#
FWH
GPIO Pin Type Function
GPIO 5 I INTH#
C
GPI 0 I ATA IDE 1 Detect C
GPIO 6 I AC97 Enabled/Disabled
GPI 1 I ATA IDE 2 Detect
GPIO 7 I None
GPI 2 I Auto Recovery
GPIO 8 I Non Connect
GPI 3 I Reserved
GPIO 9 I AC'97 Serial Data In
GPIO 10 I Non Connect
GPIO 11 I Non Connect
GPIO 12 I External SMI
DEVICE ICH INT Pin IDSEL
GPIO 13 I LPC PME
PCI Slot 1 INTA# AD16
GPIO 14~15 I Not Implemented
INTB#
B
GPIO 16 O Non Connect INTC# B
INTD#
GPIO 17 O Non Connect
GPIO 18 O Not Implemented PCI Slot 2 INTF# AD17
INTG#
GPIO 19 O Not Implemented
INTH#
GPIO 20 O Non INTE#
GPIO 21 O Vpp Programming Control
GPIO 22 O Not Implemented
GPIO 23 OD BIOS Locked/Unlocked
GPIO 24 O Non
A
GPIO 25 O Non A
GPIO 26 O Non
Micro Star Restricted Secret
GPIO 27 I/O Non Title Rev
GPIO Spec.
GPIO 28 I/O non
Document Number 0A
MS-6506
MICRO-STAR INT'L CO.,LTD. Last Revision Date:
GPIO 29~31 I/O Not Implemented
Monday, June 04, 2001
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan Sheet
http://www.msi.com.tw 3 of 32
5 4 3 2 1
8 7 6 5 4 3 2 1
*Trace less 0.5"
CLOCK GENERATOR BLOCK Shut Source Termination Resistors Pull-Down Capacitors
for good filtering from 10K~1M
CPUCLK R108 49.9RST
U10
Differential Pair CPUCLK# R107 49.9RST
FB12 39 41 R115 33 CPUCLK MCHCLK R102 49.9RST
VCC3 CPU_VDD CPU0 CPUCLK {5}
X_600S/0805 R116 33 CPUCLK# MCHCLK# R103 49.9RST
+
40 CPUCLK# {5}
CB145 Rubycon CT23 CB81 CB77 CPU0#
104P 105P 104P 36 38 R110 33 MCHCLK
CPU_GND CPU1 MCHCLK {7}
37 R111 33 MCHCLK# CN10
CPU1# MCHCLK# {7}
D ELS10/16-B X_10P-8P4C D
46 8 7
MREF_VDD C_STP MCH_66
45 Trace less 0.2" 6 5
CB86 3VMREF/CPU_STP# P_STP ICH_66
44 4 3
104P 3VMREF#/PCI_STP# AGPCLK
43 49.9ohm for 50ohm M/B impedance 2 1
MREF_GND
32 31 R117 33 MCH_66
3V66_VDD 3V66_0 MCH_66 {7}
30 R118 33 ICH_66 CN15
3V66_1 ICH_66 {10}
CB76 28 R119 33 AGPCLK X_10P-8P4C
for good filtering from 10K~1M R127 104P 29
3V66_GND
3V66_2
3V66_3
27 3V66_3 C73 10P
AGPCLK {15} CLOCK STRAPPING RESISTORS 8 7
X_0 SIO_PCLK 6 5
6 FS2 MODE 1 2 SIO_PCLK SIO_PCLK {11} FWH_PCLK 4 3
FB13 VCC3V FS2/PCI_F0 FS3 RN9
VCC3 9 7 3 4 FWH_PCLK FWH_PCLK {13}
FS4 R151 10K VCC3V ICH_PCLK 2 1
X_600S/0805 PCI_VDD FS3/PCI_F1 MODE FS2 6 ICH_PCLK FS3 R141 10K VCC3V
+
8 5 ICH_PCLK {9}
CB167 Rubycon CT24 CB98 CB91 MODE/PCI_F2 8P4R-33 CN16
7 8
104P 105P 104P 5 10 FS4 FS1 R136 X_10K VCC3V X_8P4C-10P
PCI_GND FS4/PCI0 R147 10K PCICLK0
11 7 8
ELS10/16-B PCI1 PCICLK1
18 12 5 6
PCI_VDD PCI2 PCICLK0
14 7 8 PCICLK0 {16} 3 4
CB89 PCI3 RN10 5 PCICLK1 FS0 R135 10K VCC3V
15 6 PCICLK1 {16} 1 2
104P PCI4 8P4R-33 3 R146 X_10K
13 16 4
PCI_GND PCI5 17 1 2
*Put GND copper under Clock Gen. PCI6 FS2 R140 10K VCC3V
connect to every GND pin 24
48_VDD
R139 X_10K
22 FS0 R153 33 ICH_48
* 40 mils Trace on Layer 4 CB93 FS0/48MHz FS1 R137 33 SIO_48
ICH_48 {10}
MODE R142 10K ICH_48 C93 10P
23 SIO_48 {11}
with GND copper around it 104P FS1/24_48MHz SIO_48 C89 10P
21
48_GND
* put close to every power pin
C 2 C
REF_VDD MUL0 R120 33 ICH_14 MUL0 R106 X_10K VCC3V
* Trace Width 7mils. 48 ICH_14 {10}
CB95 MUL0/REF0 MUL1 R105 10K
1
104P 47 MUL1/REF1
* Same Group spacing 15mils REF_GND MUL1 R149 X_10K VCC3V ICH_14 C74 10P
34 3 C81 18P R150 10K
* Different Group spacing 30mils CORE_VDD X1 32pF
CB78 X1 14.318MHZ/32PF
* Different mode spacing 7mils on itself 104P C78 18P SMBCLK R101 4.7K
33 4 VCC3
CORE_GND X2 SMBDATA R109 4.7K
SMBCLK 26 35 R104 475RST
{10,11,13,14} SMBCLK SCLK IREF
SMBDATA 25 used only for EMI issue
{10,11,13,14} SMBDATA SDATA CRST#
20 R134 10K C_STP R112 X_1K VCC3V
R148 VTT_GD# 19 RST# 42 R114 4.7K P_STP R113 X_1K
VCC3
10K VTT_GD# PWR_DN# VCC3V Trace less 0.2"
C
ICS950208
B Q19 ICS950208
VCCP
2N3904S CY28324
R157 220
E
PRIMARY IDE BLOCK SECONDARY IDE BLOCK
ATA100 IDE CONNECTORS
R186 4.7K IDE1 R172 4.7K IDE2
B
YJ220-CB-1 YJ220-CW-1 B
HD_RST# R185 33 1 2 HD_RST# R189 33 1 2
PDD7 3 4 PDD8 SDD7 3 4 SDD8
{10} PDD[0..7] PDD[8..15] {10} {10} SDD[0..7] SDD[8..15] {10}
PDD6 5 6 PDD9 SDD6 5 6 SDD9
PDD5 7 8 PDD10 SDD5 7 8 SDD10
PDD4 9 10 PDD11 SDD4 9 10 SDD11
PDD3 11 12 PDD12 SDD3 11 12 SDD12
PDD2 13 14 PDD13 SDD2 13 14 SDD13
PDD1 15 16 PDD14 SDD1 15 16 SDD14
PDD0 17 18 PDD15 SDD0 17 18 SDD15
19 19
{10} PD_DREQ 21 22 {10} SD_DREQ 21 22
{10} PD_IOW# 23 24 {10} SD_IOW# 23 24
{10} PD_IOR# 25 26 {10} SD_IOR# 25 26
27 28 R125 470 27 28 R128 470
{10} PD_IORDY {10} SD_IORDY
{10} PD_DACK# 29 30 {10} SD_DACK# 29 30
{9} IRQ14 31 32 {9} IRQ15 31 32
{10} PD_A1 33 34 PD_DET {13} {10} SD_A1 33 34 SD_DET {13}
{10} PD_A0 35 36 PD_A2 {10} {10} SD_A0 35 36 SD_A2 {10}
{10} PD_CS#1 37 38 PD_CS#3 {10} {10} SD_CS#1 37 38 SD_CS#3 {10}
{17} PD_LED 39 40 {17} SD_LED 39 40
C75 R122 C77 R121
R187 8.2K 220P 8.2K R100 8.2K 220P 8.2K
VCC5 VCC5
VCC3 VCC3
A A
PCIRST# 9 8 HD_RST# R300 1K
RESET BLOCK VCC5
U18D
R327 330
7407S
(VCC5_SB) R328 330
Micro Star Restricted Secret
VCC3 VCC3
Title Rev
{9} PCIRST# PCIRST# 1 2 PCIRST#1 {7,11,13} PCIRST# 3 4 PCIRST#2 {15,16} Clock CY28323/4 & ATA100 IDE
Document Number 0A
U18A U18B MS-6506
7407S C173 7407S MICRO-STAR INT'L CO.,LTD. Last Revision Date:
(VCC5_SB) (VCC5_SB) Monday, June 04, 2001
X_10P No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan Sheet
http://www.msi.com.tw 4 of 32
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CPU SIGNAL BLOCK CPU GTL REFERNCE VOLTAGE BLOCK
VCCP
VCCPS+ {20}
{7} HA#[3..31] VCCPS- {20}
Length < 1.5inch. R86
VID[0..4] {11,20} 2/3*Vccp 49.9RST
ITP_DBR#
GTLREF1
HA#31
HA#30
HA#29
HA#28
HA#27
HA#26
HA#25
HA#24
HA#23
HA#22
HA#21
HA#20
HA#19
HA#18
HA#17
HA#16
HA#15
HA#14
HA#13
HA#12
HA#11
HA#10
HA#9
HA#8
HA#7
HA#6
HA#5
HA#4
HA#3
D C44 C43 C53 R87 D
AE3 VID2
AE4 VID1
AE5 VID0
AE1 VID4
AE2 VID3
220P 220P 105P 100RST
AD26
AC26
AE25
AB1
W2
W1