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A B C D E




1 1




Compal Confidential
2
Schematics Document 2




AUBURNDALE/CLARKSFIELD with
Intel IBEX PEAK-M core logic

3
Dior DIS 3




2008-10-30
REV:0.1



4 4




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 30, 2008 Sheet 1 of 50
A B C D E
A B C D E



Compal Confidential
File Name : Dior DIS

Thermal Sensor
Fan Control
DP to Docking
Page 33
Dior DIS XDP Conn.
Page 4
Accelerometer

LIS302DLTR
Page 4
ADM1032 Page 23 Mobile Page 31

1 1
ATI M92S/M93S PEG CPU Dual Core DDR3 1066/1333MHz 1.5V DDR3-SO-DIMM X 2
LCD conn
Page 20 BANK 0, 1, 2, 3 Page 9,10


CRT Page 21,22,23,24,25 Socket-rPGA989 Dual Channel
Page 19 37.5mm*37.5mm

Page 4,5,6,7,8
CRT to Docking VRAM*4 CK505
Page 33
DMI X4 Clock Generator
HDMI conn Page 26 ICS9LPRS397
Page 23
Page 11
USB x2(Docking) Page 34

USB x2(Sub/B) Page 34
2
Express Card 54 WWAN Card Mini-Card 2


Sub-board UWB USB2.0 FingerPrinter VFM451 daughter board
Page 34 Page 29 Page 29
Intel Ibex Peak M USBx1 Page 34
Azalia
USB conn x 2(For I/O)
PCI-E BUS 1071pins BT Conn USB x 1 Page 31
25mm*27mm SATA0

USB x1(Camara)
10/100/1000 LAN WLAN Card 1394/Card Reader SATA1 Page 20
Page 12,13,14,15,16,17
Marvell Sub-board MDC V1.5 RJ11
88E8072/88E8075 Page 29 ONFI Interface Page 30 Page 30
Page 27 Page 34

Braidwood Audio CKT 92HD75 TPA6047A
Sub-board Page 34 AMP & Audio Jack Page 34
Page 18
RJ45 CONN
3
1394 port SD/MMC/ 3

Page 28
MS/XD Slot SATA ODD Connector Page. 33
Page 18 Docking CONN.
NAND card
2.5" SATA HDD Connector (2) PS/2 Interfaces
LPC BUS Page 18 (2) USB 2.channels
(2) SATA Channels
RTC CKT. (2) Display Port Channels
LED (1) Serial Port
Page 34 Page 34 (1) Parallel Port
(1) Line In
(1) Line Out
SMSC KBC Super I/O
Power OK CKT. TPM1.2 (1) RJ45 (10/100/1000)
Page 37
SLB9635TT 1098 IT8305E Page 36
(1) VGA
Page 32 page 35 (1) 2 LAN indicator LED's
(1) Power Button
COM1 LPT (1) I2C interface
4
Power On/Off CKT. Touch Pad CONN. Int.KBD ( Docking ) ( Docking )
4


Page 34 Page 33 Page 33
Page 30 Page 30

TrackPoint CONN.
Page 30
Security Classification Compal Secret Data Compal Electronics, Inc.
2008/10/24 2009/10/24 Title
DC/DC Interface CKT. Issued Date Deciphered Date
Block Diagram
Page 38 SPI ROM THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number
Custom LA-4891
Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4MB Page 32 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 2 of 50
A B C D E
A




( O MEANS ON X MEANS OFF )
Voltage Rails Symbol Note :

+RTCVCC +B +5VALW +1.5V +5VS : means Digital Ground
+3VL +3VALW +0.75V +3VS
+1.5VS
power
plane +NVVDD : means Analog Ground
+VCCP
+CPU_CORE
+1.05VS
+1.8VS


State



Install below 43 level BOM structure for ver. 0.1
[email protected] : means just build when PCIE port 80 CARD function enable. Remove before MP
S0
O O O O O [email protected] : Install for M92 Graphic controller
S1 [email protected] : Install for 8072 NIC controller
O O O O O
S3 [email protected] : Install for 1098 KBC controller
O O O O X
[email protected] : Install for 32 pin CLOCK GEN
S5 S4/AC
O O O X X
Install below 45 level BOM structure for ver. 0.1
S5 S4/ Battery only
O O X X X [email protected] : means just put it in the BOM of 45 level.
S5 S4/AC & Battery
don't exist
O X X X X
1 1




Reserve below BOM structure for ver. 0.1
@ : means just reserve , no build
[email protected] : means ME part.
[email protected] : Install for M93 Graphic controller
[email protected] : Install for 8075 NIC controller
SMBUS Control Table [email protected] : Install for 1091 KBC controller

THERMAL [email protected] : Install for 72 pin CLOCK GEN
SOURCE BATT XDP SODIMM CLK CHIP MINI CARD DOCK NIC SENSOR G-SENSOR


SMB_EC_CK1
SMB_EC_DA1
SMSC1098
V X X X X X X X X
SMBCLK
SMBDATA
Calpella X V V V V V V X V
SML0CLK
SML0DATA
Calpella X X X X X X X X X
SML1CLK
SML1DATA
Calpella X X X X X X X V X




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/24 Deciphered Date 2009/10/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4891 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 27, 2008 Sheet 3 of 50
A
5 4 3 2 1


Layout rule10mil width trace +VCCP
length < 0.5", spacing 20mil PM_EXTTS#0 1 2 +VCCP
JCPU1B R1 10K_0402_5%
20_0402_1% 1 R2 2COMP3 AT23 1 4 RP2 PM_EXTTS#1 1 2 XDP_TDI_R 1 2
COMP3 CLK_CPU_BCLK_P 15
A16 CLK_BCLK 2 3 R7 10K_0402_5% R8 @ 51_0402_5%
BCLK CLK_CPU_BCLK#_P 15




MISC
20_0402_1% 1 R9 2COMP2 AT24 COMP2 BCLK# B16 CLK_BCLK# 0_4P2R_5% XDP_TMS 1 2
[email protected] R10 @ 51_0402_5%
49.9_0402_1% 1 R3 2COMP1 CLK_CPU_XDP XDP_PREQ#




CLOCKS
G16 COMP1 BCLK_ITP AR30 1 2
AT30 CLK_CPU_XDP# R4 @ 51_0402_5%
49.9_0402_1% BCLK_ITP#
1 R5 2COMP0 AT26 COMP0
XDP_TDO 1 2
E16 CLK_PEG 1 4 RP4 R6 51_0402_5%
PEG_CLK CLK_EXP 13 This shall place near XDP
D16 CLK_PEG# 2 3
PEG_CLK# CLK_EXP# 13 +1.5V
PAD T1 TP_SKTOCC# AH24 R40 0_0402_5% 0_4P2R_5%
SKTOCC# [email protected] XDP_TCK
DPLL_REF_SSCLK A18 1 2 1 2
D A17 1 2 VDDPWRGOOD_R 1 2 R11 @ 51_0402_5% D
H_CATERR# DPLL_REF_SSCLK# R39 0_0402_5% R12 4.75K_0402_1%
AK14 CATERR# This shall place near CPU




THERMAL
1 2
R13 12K_0402_1%
SM_DRAMRST# F6 DRAMRST# 9,10
15 H_PECI 1 R14 2 H_PECI_ISO AT15 PECI
0_0402_5% AL1 SM_RCOMP0
SM_RCOMP[0] SM_RCOMP1
AM1

1 R15 2 H_PROCHOT#_D AN26
SM_RCOMP[1]
SM_RCOMP[2] AN1 SM_RCOMP2 XDP Connector
47 H_PROCHOT# PROCHOT#
0_0402_5% AN15 PM_EXTTS#0 T91 PAD
PM_EXT_TS#[0]




DDR3
MISC
AP15 PM_EXTTS#1 1 2 from DDR JP1
PM_EXT_TS#[1] PM_EXTTS#1_R 9,10
R17 0_0402_5% 1 2
GND0 GND1
15 H_THERMTRIP# 1 R19 2 H_THERMTRIP#_R AK15 THERMTRIP#
XDP_PREQ# 3 OBSFN_A0 OBSFN_C0 4
0_0402_5% XDP_PRDY# 5 6
OBSFN_A1 OBSFN_C1
7 GND2 GND3 8
AT28 XDP_PRDY# XDP_BPM#0 9 10
PRDY# XDP_PREQ# XDP_BPM#1 OBSDATA_A0 OBSDATA_C0
PREQ# AP27 11 OBSDATA_A1 OBSDATA_C1 12
+VCCP 13 14 +VCCP
XDP_TCK XDP_BPM#2 GND4 GND5
TCK AN28 15 OBSDATA_A2 OBSDATA_C2 16
H_CPURST# 1 R18 2H_CPURST#_R AP26 AP28 XDP_TMS XDP_BPM#3 17 18
RESET_OBS# TMS OBSDATA_A3 OBSDATA_C3




PWR MANAGEMENT
0_0402_5% AT27 XDP_TRST# 19 20
TRST# GND6 GND7 +3VS




JTAG & BPM
21 OBSFN_B0 OBSFN_D0 22
14 H_PM_SYNC 1 R20 2 H_PM_SYNC_R AL15 PM_SYNC TDI AT29 XDP_TDI_R 1 23 OBSFN_B1 OBSFN_D1 24
0_0402_5% AR27 XDP_TDO_R 25 26
TDO XDP_TDI_M C1 XDP_BPM#4 GND8 GND9
TDI_M AR29 27 OBSDATA_B0 OBSDATA_D0 28




2
H_CPUPWRGD 1 R21 2 VCCPWRGOOD_1 AN14 AP29 XDP_TDO_M 0.1U_0402_10V6K XDP_BPM#5 29 30
0_0402_5% VCCPWRGOOD_1 TDO_M @ 2 OBSDATA_B1 OBSDATA_D1 R22
31 GND10 GND11 32
AN25 XDP_DBRESET# XDP_BPM#6 33 34 1K_0402_5%
DBR# OBSDATA_B2 OBSDATA_D2
15 H_CPUPWRGD 1 R23 2 VCCPWRGOOD_0 AN27 VCCPWRGOOD_0
R24 XDP_BPM#7 35 OBSDATA_B3 OBSDATA_D3 36
0_0402_5% 1K_0402_5% 37 38




1
XDP_BPM#0 H_CPUPWRGD H_CPUPWRGD_R GND12 GND13 CLK_CPU_XDP
BPM#[0] AJ22 1 2 39 PWRGOOD/HOOK0 ITPCLK/HOOK4 40
C 1 R25 2 VDDPWRGOOD_R AK13 AK22 XDP_BPM#1 PM_PWRBTN#_R 41 42 CLK_CPU_XDP# C
14 PM_DRAM_PWRGD SM_DRAMPWROK BPM#[1] 14 PM_PWRBTN#_R HOOK1 ITPCLK#/HOOK5
0_0402_5% AK24 XDP_BPM#2 43 44 1K_0402_5%
BPM#[2] XDP_BPM#3 H_PWRGD_XDP VCC_OBS_AB VCC_OBS_CD XDP_RST#_R R27 H_CPURST#
BPM#[3] AJ24 1 2 45 HOOK2 RESET#/HOOK6 46 1 2
37 VTTPWRGOOD AM15 AJ25 XDP_BPM#4 R26 0_0402_5% 47 48 XDP_DBRESET#
VTTPWRGOOD BPM#[4] HOOK3 DBR#/HOOK7 XDP_DBRESET# 12,14
AH22 XDP_BPM#5 49 50
BPM#[5] XDP_BPM#6 GND14 GND15 XDP_TDO
BPM#[6] AK23 9,10,11,13,27,29,31,33 SMB_DATA_S3 51 SDA TD0 52
H_PWRGD_XDP 1 R29 2 H_PWRGD_XDP_R AM26 AH23 XDP_BPM#7 9,10,11,13,27,29,31,33 SMB_CLK_S3 53 54 XDP_TRST#
0_0402_5% TAPPWRGOOD BPM#[7] SCL TRST# XDP_TDI
55 TCK1 TDI 56
XDP_TCK 57 58 XDP_TMS
PLT_RST#_R +VCCP TCK0 TMS
15 BUF_PLT_RST# 1 R30 2 AL14 RSTIN# 59 GND16 GND17 60
24.9K_0402_1%
10/09 HP SAMTE_BSH-030-01-L-D-A [email protected]
1




2
XDP_RST#_R 1 @ 2 PLT_RST# PLT_RST# 12,15,21,27,29,32,34
IC,AUB_CFD_rPGA,R1P0 R48 R31 0_0402_5%
R32 1K_0402_5%
12.4K_0402_1%
2




1
PM_PWRBTN#_R



Processor Pullups JTAG MAPPING

+VCCP XDP_TDI_R 1 2 XDP_TDI