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5 4 3 2 1


2008.06.01
VTERM(+0.9V) Mariana Block Diagram C Stage
VTT(+1.05V)
+1.5VSUS VID[0:6] CPU VCORE
+1.5V XDP Diamondville
D IMVP 6 D

+1.8VSUS FCBGA8 437
+1.8V VCORE:+1.196 ~ +0.748 +/- CPU_CLK
+2.5V Thermal VCCP:+1.05V
VCCA:+1.8V or +1.5V
Clock Gengerator
3VPCU Sensor +/- HCLK CK505M
+3.3V FSB 533MHz
+3.3VSUS
LCD_3.3V 8.9" or 12" LVDS
LCD_5V LCD DDR2 DDR2 400/533
+5V 945GMS/GSE CHB 400/533 CHA
RGB
512MB DOWN
C
CRT FCBGA 998 SO-DIMM C


RANK 1
RANK 2
(Up to 1GB) 64M X 16 X 4
10/100 Ethernet PCI-e X2 DMI
RJ-45 SATA
BCM5906 2.5" HDD
IDE SSD 4/8/16GB
(Option)
HP/Mic HDA CODEC HD Audio
Audio ALC269 ICH7M PCI-e/USB
Mini PCIe Slot WLAN / WWAN
B Module B

Jack
Int.
Amplify BGA 652 USB Card Reader 4 in 1 Socket
Int. Mic SPK PCI-e
RTL5158E SD/MMC/MS/MS-Pro
USB
USB PORT X 2
34mm New Card LPC BUS
USB Camera Module
ENE Camera Conn. (Option)
SPI
KB3310 Flash USB
A
Bluetooth A

(Option)

Quanta Computer Inc.
Int. KB T/P Battery Charger PROJECT : FL1
Size Document Number Rev
1A
Block Diagram
Date: Saturday, June 07, 2008 Sheet 1 of 34
5 4 3 2 1
1 2 3 4 5 6 7 8


Table of Contents Power States
CONTROL
PAGE DESCRIPTION POWER PLANE VOLTAGE PAGE DESCRIPTION ACTIVE IN
SIGNAL
1 Schematic Block Diagram
2 VIN 10V~+19V

5VPCU

A 3VPCU A




B B




C C



GND PLANE PAGE DESCRIPTION

GND ALL




D D




Quanta Computer Inc.
PROJECT : FL1
Size Document Number Rev
1A
POWER MANAGER
Date: Saturday, June 07, 2008 Sheet 2 of 34
1 2 3 4 5 6 7 8
5 4 3 2 1




D D




Adapter


Charger VIN
MB39A129
MAINON
S4# S3#


Battery
TI
MAXIM RealTek MAXIM
TPS51116 MAX8796
C MAX17020 LDO RT8204 C



9A 0.9A 6A 3A IMVP_VR_ON
4A 3V_ALW_ON 4A 5V_ALW_ON

+15V_ALW 3VPCU 5VPCU VCC18MEM VTERM(0.9V) +1.05V_VCCP +VCC_CORE




MOSFET

4A
MAINON MAINON 3VSUSON 3VSUSON MAINON USBON

+1.5V
B B
LDO MOSFET LDO LDO MOSFET SW IC

0.16A 3A 0.33A 0.02A 1.7A 2A


+2.5V +3.3V +3.3VSUS +5VSUS +5V 5VUSB

0.35A


LCD_3.3V




A A




Quanta Computer Inc.
PROJECT : FL1
Size Document Number Rev
1A
Power Block Diagram
Date: Saturday, June 07, 2008 Sheet 3 of 34
5 4 3 2 1
5 4 3 2 1




+3.3V


+1.05V_VDD PM_STPPCI# R314 2.2K_4

+3.3V C495 L39 +1.05V
L41 0.1U/10V_4 PBY160808T-301Y-N_6 PM_STPCPU# R323 2.2K_4
PBY160808T-301Y-N_6 C487 C504 C464 C497 C494 C498 C482 C472 C471
0.1U/10V_4
D D
C469 10U/10V_8 10U/10V_8 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 MINI_CLK_REQ#_R R336 10K_4
10U/10V_8
C496 U24
0.1U/10V_4 VDD_CK_VDD_PCI 9 55 NEW_CLK_REQ#_R R296 10K_4
C479 VDD_CK_VDD_48 VDD_PCI IO_VOUT
16 VDD_48
0.1U/10V_4 VDD_CK_VDD_PCI 23 7 G1_SMBCK1
C473 VDD_CK_VDD_REF VDD_PLL3 SCLK G1_SMBDT1 LAN_CLK_REQ#_R R342 10K_4
4 VDD_REF SDA 6
0.1U/10V_4 CK505
C478 VDD_CK_VDD_PCI 46 45 PM_STPPCI# PM_STPPCI# (14)
0.1U/10V_4 VDD_CK_VDD_CPU VDD_SRC SRC5/PCI_STOP# PM_STPCPU# LCLK_EC C489 *33P/50V_4
62 VDD_CPU SRC5#/CPU_STOP# 44 PM_STPCPU# (14) To SB
+1.05V_VDD
C486 19 61 CLK_CPU_BCLK
VDD_96_IO CPU0 CLK_CPU_BCLK (5)
27 60 CLK_CPU_BCLK# To CPU CLKUSB_48 C516 15P/50V_4
VDD_PLL3_IO CPU0# CLK_CPU_BCLK# (5)
10U/10V_8 33 VDD_SRC_IO_1 CLK_MCH_BCLK
52 VDD_SRC_IO_3 CPU1 58 CLK_MCH_BCLK (7)
43 57 CLK_MCH_BCLK# To NB 14M_ICH C481 *33P/50V_4
VDD_SRC_IO_2 CPU1# CLK_MCH_BCLK# (7)
56 VDD_CPU_IO
54 CLK_PCIE_MINI2&4_R T79
SRC8/ITP CLK_PCIE_MINI2&4#_R T78 PCLK_ICH C491 *33P/50V_4
SRC8#/ITP# 53

R331 33_4 PCLK_DEBUG_R 8 42 CLK_PCIE_3GPLL#
(21) PCLK_DEBUG PCI0/CR#_A SRC10# CLK_PCIE_3GPLL# (8)
41 CLK_PCIE_3GPLL To NB
SRC10 CLK_PCIE_3GPLL (8)
LAN_CLK_REQ#_R 10
(23) LAN_CLK_REQ# R343 475/F_4 PCI1/CR#_B CLK_MCH_OE#_R R334 475/F_4
SRC11/CR#_H 40 MCH_CLKREQ# (8)
PCLK_OZ129_R 11 39 MINI_CLK_REQ#_R R335 475/F_4 MINI_CLK_REQ# (26)
PCI2/TME SRC11#/CR#_G
T91 PCI_CLK_SIO_R 12 37 CLK_PCIE_MINI+
PCI3 SRC9 CLK_PCIE_MINI+ (26)
38 CLK_PCIE_MINI- To WLAN
SRC9# CLK_PCIE_MINI- (26)
LCLK_EC R346 33_4 LCLK_EC_R 13
(21) LCLK_EC PCI4/SRC5_EN
C
SRC7/CR#_F 51 C
PCLK_ICH R351 33_4 PCLK_ICH_R 14 50 NEW_CLK_REQ#_R R301 475/F_4 NEW_CLK_REQ# (25)
(13) PCLK_ICH PCIF5/ITP_EN SRC7#/CR#_E
SEL2 SEL1 SEL0 Frequence select
CG_XIN 3 48 CLK_PCIE_NEW+
XTAL_IN SRC6 CLK_PCIE_NEW+ (25)
47 CLK_PCIE_NEW- To New Card FSC FSB FSA CPU SRC PCI
SRC6# CLK_PCIE_NEW- (25)
CG_XOUT 2
R367 22_4 XTAL_OUT CLK_PCIE_LAN+
(20) CLK_CR_48M R368 22_4 FSA SRC4 34
CLK_PCIE_LAN-
CLK_PCIE_LAN+ (23) 1 0 1 100 100 33
(14) CLKUSB_48 17 USB_48/FSA SRC4# 35 CLK_PCIE_LAN- (23) To LAN
CLK_BSEL0 R369 2.2K_4 0 0 1 133 100 33 Default
CLK_BSEL1 FSB 64 31 CLK_PCIE_ICH
FSB/TEST/MODE SRC3/CR#_C CLK_PCIE_ICH (13)
CLK_BSEL2 R321 10K_4 32 CLK_PCIE_ICH# To SB 0 1 1 166 100 33
SRC3#/CR#_D CLK_PCIE_ICH# (13)
R325 33_4 FSC 5
(14) 14M_ICH REF0/FSC/TESTSEL
65 28 CLK_PCIE_SATA 0 1 0 200 100 33
VSS_BODY SRC2/SATA CLK_PCIE_SATA (12)
15 29 CLK_PCIE_SATA# To SB
VSS_PCI SRC2#/SATA# CLK_PCIE_SATA# (12)
C477 18 0 0 0 266 100 33
27P/50V_4 CG_XIN VSS_48 DREFSSCLK
22 VSS_IO SRC1/SE1 24 DREFSSCLK (8)
26 25 DREFSSCLK# To NB 1 0 0 333 100 33
VSS_PLL3 SRC1#/SE2 DREFSSCLK# (8)
2




Y3 59 VSS_CPU DREFCLK
CL=20p 30 VSS_SRC1 SRC0/DOT96 20 DREFCLK (8) 1 1 0 400 100 33
14.318MHZ 36 21 DREFCLK# To NB
VSS_SRC2 SRC0#/DOT96# DREFCLK# (8)
C476 49 1 1 1 Reserved
1




27P/50V_4 CG_XOUT VSS_SRC3
1 VSS_REF CKPWRGD/PWRDWN# 63 VR_PWRGD_CK505 (14)
SLG8SP513 +1.05V R371 56_4
SLG8SP513VTR ,ICS9LPRS365BKLFT To NB
+3.3V R341 *10K_4 PCLK_OZ129_R R373 *0_4 CLK_BSEL0 R372 1K_4 MCH_BSEL0 (8)
(5) CPU_BSEL0
ICS9LPRS365 RTM875T-606 R370 *1K_4
(ALPRS365K13) (AL000875K06) PULL HIGH PULL DOWN R340 *10K_4
B B
+1.05V R298 *1K_4
PCI2/TME
Pin 11 PCI2/TME internal PD NO OVERCLOCKING (default) NORMAL RUN
+3.3V R348 *10K_4 LCLK_EC_R R302 *0_4 CLK_BSEL1 R299 1K_4 MCH_BSEL1 (8)
PCI-3/SRC5_EN PIN37/38 IS HIGH 27MHz (5) CPU_BSEL1
Pin 12 PCI-3 internal PD PIN37/38 IS SRC5 PCI_STOP/CPU_STOP (default) LOW SRC R308 0_4
R347 *10K_4
PCI-4/27M_SEL PIN 17/18 R317 *1K_4
+1.05V
Pin 13 PCI-4/27M_SEL internal PD PIN 17/18 IS 27MHz IS SRC/DOT (default)
+3.3V R353 *10K_4 PCLK_ICH_R
PCIF-5/ITP_EN R318 *0_4 CLK_BSEL2 R312 1K_4
Pin 14 PCIF-5/ITP_EN internal PD PIN 46/47 IS CPUITP PIN 46/47 IS SRC8 (default) (5) CPU_BSEL2 MCH_BSEL2 (8)
R352 *10K_4 R316 0_4




+3.3V +3.3V
Clock Gen I2C
:ICS9LPRS365BGLFT QCI:ALPRS365K13
:SLG8SP512TTR: QCI:AL8SP512K05

R328 R329
4.7K_4 4.7K_4
2




2




Q36 Q37

3 1 G1_SMBDT1 3 1 G1_SMBCK1
(14) SMBDT G1_SMBDT1 (15,17,25,26) (14) SMBCK G1_SMBCK1 (15,17,25,26)

A 2N7002E 2N7002E A



SM_BUS_Group1
1. Clock Gen
2. Memory Rom Quanta Computer Inc.
3. Mini Card PROJECT : FL1
4. New Card Size Document Number Rev
5. CPU Thermal Monitor 1A
CLOCK GENERATOR
Date: Saturday, June 07, 2008 Sheet 4 of 34
5 4 3 2 1
5 4 3 2 1




U12A U12B
D (7) H_A#[31:3] (7) H_D#[63:0] H_D#[63:0] (7) D
H_A#3 P21 V19 H_D#0 Y11 R3 H_D#32
A[3]# ADS# H_ADS# (7) D[0]# D[32]#
H_A#4 H20 Y19 H_D#1 W10 R2 H_D#33
A[4]# BNR# H_BNR# (7) D[1]# D[33]#
H_A#5 N20 U21 H_D#2 Y12 P1 H_D#34
A[5]# BPRI# H_BPRI# (7) D[2]# D[34]#
H_A#6 R20 H_D#3 AA14 N1 H_D#35
A[6]# D[3]# D[35]#




0
GROUP
ADDR




DATA GRP 0
H_A#7 J19 T21 H_D#4 AA11 M2 H_D#36
A[7]# DEFER# H_DEFER# (7) D[4]# D[36]#
H_A#8 N19 T19 H_D#5 W12 P2 H_D#37
A[8]# DRDY# H_DRDY# (7) D[5]# D[37]#
H_A#9 G20 Y18 H_D#6 AA16 J3 H_D#38
H_DBSY# (7)




DATA GRP 2
H_A#10 A[9]# DBSY# H_D#7 D[6]# D[38]# H_D#39
M19 A[10]# Y10 D[7]# D[39]# N3
H_A#11 H21 T20 H_D#8 Y9 G3 H_D#40
A[11]# BR0# H_BREQ#0 (7) D[8]# D[40]#
H_A#12 L20 H_D#9 Y13 H2 H_D#41
A[12]# D[9]# D[41]#




CONTROL
H_A#13 M20 F16 IERR# R31 56_4 +1.05V H_D#10 W15 N2 H_D#42
H_A#14 A[13]# IERR# D[10]# D[42]#
K19 A[14]# INIT# V16 H_INIT#R R54 H_INIT# (12)
H_D#11 AA13 D[11]# D[43]# L2 H_D#43
H_A#15 J20 1K/F_4 R56 330_4 +1.05V H_D#12 Y16 M3 H_D#44
H_A#16 A[15]# H_D#13 D[12]# D[44]# H_D#45
L21 A[16]# LOCK# W20 H_LOCK# (7) W13 D[13]# D[45]# J2
K20 H_D#14 AA9 H1 H_D#46
(7) H_ADSTB#0 ADSTB[0]# H_CPURST# (7) D[14]# D[46]#
T1 H_AP0 D17 D15 H_D#15 W9 J1 H_D#47
(7) H_REQ#[4:0] AP0 RESET# H_RS#[2:0] (7) D[15]# D[47]#
H_REQ#0 N21 W18 H_RS#0 Y14 K2
REQ[0]# RS[0]# (7) H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 (7)
H_REQ#1 J21 Y17 H_RS#1 Y15 K3
REQ[1]# RS[1]# (7) H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 (7)
H_REQ#2 G19 U20 H_RS#2 W16 L1
REQ[2]# RS[2]# (7) H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 (7)
H_REQ#3 P20 W19 T16 H_DP#0 V9 M4 H_DP#2 T10
REQ[3]# TRDY# H_TRDY# (7) DP#0 DP#2
H_REQ#4 R19
REQ[4]# (7) H_D#[63:0] H_D#[63:0] (7)
AA17 H_D#16 AA5 C2 H_D#48
(7) H_A#[31:3] HIT# H_HIT# (7) D[16]# D[48]#
H_A#17 C19 V20 H_D#17 Y8 G2 H_D#49
A[17]# HITM# H_HITM# (7) D[17]# D[49]#
H_A#18 F19 H_D#18 W3 F1 H_D#50
H_A#19 A[18]# XDP_BPM#0 T7 H_D#19 D[18]# D[50]# H_D#51
E21 A[19]# BPM[0]# K17 U1 D[19]# D[51]# D3
H_A#20 A16 J18 XDP_BPM#1 T3 H_D#20 W7 B4 H_D#52
A[20]# BPM[1]# D[20]# D[52]#




DATA GRP 1
H_A#21 D19 H15 XDP_BPM#2 T4 H_D#21 W6 E1 H_D#53
H_A#22 A[21]# BPM[2]# XDP_BPM#3 T6 H_D#22 D[21]# D[53]# H_D#54
C14 A[22]# BPM[3]# J15 Y7 D[22]# D[54]# A5


ADDR GROUP 1
H_A#23 XDP_BPM#4 T5 H_D#23 H_D#55




DATA GRP 3
C18 K18 AA6 C3




XDP/ITP SIGNALS
H_A#24 A[23]# PRDY# XDP_BPM#5 H_D#24 D[23]# D[55]# H_D#56
C C20 A[24]# PREQ# J16 Y3 D[24]# D[56]# A6 C
H_A#25 E20 M17 XDP_TCK H_D#25 W2 F2 H_D#57
H_A#26 A[25]# TCK XDP_TDI H_D#26 D[25]# D[57]# H_D#58
D20 A[26]# TDI N16 ?? V3 D[26]# D[58]# C6
H_A#27 B18 M16 XDP_TDO T11 H_D#27 U2 B6 H_D#59
H_A#28 A[27]# TDO XDP_TMS H_D#28 D[27]# D[59]# H_D#60
C15 A[28]# TMS L17 T3 D[28]# D[60]# B3
H_A#29 B16 K16 XDP_TRST# H_D#29 AA8 C4 H_D#61
H_A#30 A[29]# TRST# BR1# R51 H_D#30 D[29]# D[61]# H_D#62
B17 A[30]# BR1# V15 PM_SYSRST# (14) V2 D[30]# D[62]# C7
H_A#31 C16 *0_4 R30 R29 +1.05V H_D#31 W4 D2 H_D#63