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A B C D E




1 1




Compal confidential
2



Liverpool/Sunderland 10ATG 2




NSWAE/NTWAE LA-5331P Schematics Document
Mobile AMD S1G3/
RX881
3
SB710 3




2009-10-02 Rev. 1.0




4 4




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008-09-25 Deciphered Date 2009-09-25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, M/B LA-5331P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401716 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 23, 2010 Sheet 1 of 54
A B C D E
A B C D E




Compal Confidential
A M D S1G2 T h e r m al F a n C o n tr o l
M o d el N a m e : N S W A E / N T W A E V G A o n b o a r d CPU S e n s or
uFCPGA-638 Package ADM1032ARM-1 page 7 APL5607KI-TRG page 5
F il e N a m e : L A - 5 3 3 1 P
T i g ris P l a tf o r m page 5,6,7,8
1 H y p e r T r a n s p o rt L i n k 1


2.6 G H z
16X16
2 0 0 p i n D D R II- S O - D I M M
A TI
XBANK 0, 1, 2, 3
2
M 92
with VRAM
A TI page 9,10
Page 36,37,38,39,40,41, 42,43,44

M e m o ry
B u aSl D D R II
DU
CRT








page 17
RX881
1 .h aV n n eDl R II
C8 D
6 6 7/8 0 0 M H Z
LCD
C o n n.
page 18

H D MI C E C H D MI
EC SMBUS
C o n tr o ll e r C o n n.
R5F211B4D33SP page 19 page 19

2
PCIe 3x 1.5V 2.5GHz(250MB/s) page 11,12,13,14,15 2




A - Lin k E x p r e s s
I4I X P C I- E
R ig h t U S B I n t. C a m e r a B lu e t o o t h
C onn
USB Port 0,1 page 31 USBPort 9 page 18 USBPort 6 page 31
A TI
R TL8103EL LA N P C I e M ini C a r d NE W USB 5V 480MHz
SB710 USB 5x

1 0/1 0 0 M
PCIe port 3 page 26 W LA N
USB port 8
C ard
USB port 5
5V 480MHz
PCIe Port 2 page 27 PCIe port 0 page 27

SATA 5V 1.5GHz(150MB/s) W LA N F i n g e r P ri n t e r R T S5159E 3IN1
3IN1
R J45 eSATA USBPort 8 page 27 USBPort 7 page 31 USBPort 4 page 28 page 28
page 26 USB port 2
USB 5V 480MHz
SATA port 2 page 25
SATA
SATA
3
5V 1.5GHz(150MB/s) HDD1
SATA port 1 page 25
3

SATA
SATA
ODD
SATA port 3
page 20,21,22,23,24 page 25
C lo c k G e n e r a t o r U S B/B 5V 1.5GHz(150MB/s)
SLG8SP626VTR page 16 page 31 LPC BUS 3.3V 33 MHz


RTC P o w e r/ B HD Audio 3.3V 24.576MHz/48Mhz
C K T.
page 45 page 34
D ebug E N E K B926
P o rt D3
page 32 page 33
P o w e r O n / O ff C K T . T o u c h/ B M D C 1.5 HDA
C odec
ALC272
page 34 page 34 page 32 page 29

Touch I n t. K B D S PI
D C / D C I n t e rf a c e O D D/B
Pad RO M
page 34 page 32 page 32
C K T.
page 35 page 25
R J11 A M P LI F I E R M IC I n t. M I C HP V olu m e
TPA6017
CONN CONN C o n tr o l
page 32 page 30 page 30 page 30 page 30
page 30
P o w e r C ir c u it D C / D C
page 45,46,47,48
4 49,50,51,52 SPK 4


CONN
page 30



Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008-09-25 Deciphered Date 2009-09-25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, M/B LA-5331P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401716 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 23, 2010 Sheet 2 of 54
A B C D E
5 4 3 2 1




DESIGN CURRENT 0.1A +3VL
B+ DESIGN CURRENT 0.1A +5VL
DESIGN CURRENT 1A +3VALW
TPS51125RGER

DESIGN CURRENT 3.5A +5VALW
RUNON
D D

N-CHANNEL DESIGN CURRENT 2A +5VS
SI4800
DESIGN CURRENT 1.5A +3VS
ENVDD
RUNON P-CHANNEL DESIGN CURRENT 1A +LCD_VDD
AO3413
N-CHANNEL
SUSP
SI4800
DESIGN CURRENT 9A +1.5VS
TPS51117RGYR
NSWAE Liverpool AMD BT_PWR#
NTWAE Sunderland AMD DESIGN CURRENT 180mA +BT_VCC
P-CHANNEL
AO3413
WOL_EN#
DESIGN CURRENT 330mA +3V_LAN
P-CHANNEL
AO3413

DESIGN CURRENT 300mA +2.5VS
APL5508
POK
C C
DESIGN CURRENT 0.3A +1.2VALW
TPS51117RGYR VLDT_EN#
N-CHANNEL DESIGN CURRENT 4.5A +1.2V_HT
VR_ON
IRF8113
DESIGN CURRENT 18A +CPU_CORE_0
DESIGN CURRENT 18A +CPU_CORE_1
ISL6265 DESIGN CURRENT 3A +VDDNB
SYSON
DESIGN CURRENT 7A +1.8V
TPS51117RGYR SUSP
N-CHANNEL DESIGN CURRENT 1A +1.8VS
IRF8113
SYSON#

DESIGN CURRENT 2A +0.9V
SUSP#
APL5331KAC

B DESIGN CURRENT 7A B
+NB_CORE
TPS51117RGYR
SUSP#

DESIGN CURRENT 23A +VGA_CORE
ISL6268CAZ




A A




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008-09-25 Deciphered Date 2009-09-25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, M/B LA-5331P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401716 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 23, 2010 Sheet 3 of 54
5 4 3 2 1
A B C D E



Voltage Rails Symbol Note :

O : ON
: Digital Ground
X : OFF

: Analog Ground
+5VS
1
+3VS @ : just reserve , no build 1
power
plane +2.5VS
+1.8VS DEBUG@ : reserve for debug.
+1.5VS Layout Notes
L
+1.1VS
+B +5VALW +1.8V UMA@: means for RS780M.
+VGA_CORE
+3VL +3VALW +0.9V
+1.2V_HT
+5VL +1.2VALW +0.9V
State +CPU_CORE_NB BTO (Build-To-Order) Option Table
+RTCVCC +3V_LAN
+CPU_CORE_0
Function Express card / PCMCIA BLUE TOOTH RJ11 SSD SATA ODD WiFi G- sensor 3 in 1 card reader
+CPU_CORE_1
Description (E/A) (B) (R) (S) (H)

Explain 16" 17" Half - size First Second RTS5159

S0 BTO EXPCARD@ / PCMCIA@ BT@ MDC@ SSD@ 16inch@ 17inch@ WLAN@ WIMAX@ G@ + G_1st@ G@ + G_2nd@ CARD@
O O O O
S1
O O O O Function FingerPrinter CAMERA & MIC HDMI LVDS wireset DC-IN CHIPSET
2 2

S3 Description (F) (X) (Y)
O O O X
Explain CAMERA MIC AMD(UMA) ATI VGA/B COMMON Cost down
S5 S4/AC
O O X X
BTO FP@ CAM@ MIC@ IHDMI@ HDMI@ H@ LVDSSET@ 16inch_45@ 17inch_45@ PUMA@ TIGRIS@
S5 S4/ Battery only
O X X X
SMBUS Control Table
S5 S4/AC & Battery
don't exist X X X X
CPU LCD HDMI MXM
SOURCE INVERTER BATT HDMI SODIMM CLK WLAN DDC DDC NEW Thermal
CEC THERMAL GEN CARD Sensor
I / II ROM ROM
SENSOR
EC_SMB_CK1
KB926
I2C / SMBUS ADDRESSING EC_SMB_DA1 V V
EC_SMB_CK2
KB926
EC_SMB_DA2 V V
DEVICE HEX ADDRESS
I2C_CLK
RX881
3
DDR SO-DIMM 0 A0 1010000X I2C_DATA V 3

DDR SO-DIMM 1 A2 1010001X DDC_CLK0
RX881
CLOCK GENERATOR (EXT.) D2 11010010 DDC_DATA0 V
DDC_CLK1
RX881
DDC_DATA1
SCL0
SB710
SDA0 V V V
EC SM Bus1 address EC SM Bus2 address SCL1
SB710
SDA1 V
Device HEX Address Device HEX Address
SCL2
Smart Battery 16H 0001 011X b ADI1032-1 CPU 98H 1001 100X b SB710
SDA2
HDMI-CEC 34H 0011 010X b ADI1032-2 VGA 9AH 1001 101X b
SCL3
EC KB926D4 EC KB926D3 SB710
SDA3




4 4




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008-09-25 Deciphered Date 2009-09-25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, M/B LA-5331P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401716 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 23, 2010 Sheet 4 of 54
A B C D E
A B C D E


< C1, C2 and C7 must be replaced to 10-uF for Caspian compatibility >

+1.2V_HT
VLDT CAP. Near CPU Socket
250 mil
1 1 1 1 1 1
C3 C4 C5 C6
C1 C2
10U_0805_10V6K 10U_0805_10V6K 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
2 2 2 2 2 2

1 1




H_CADIP[0..15] H_CADOP[0..15]
11 H_CADIP[0..15] H_CADOP[0..15] 11
H_CADIN[0..15] H_CADON[0..15]
11 H_CADIN[0..15] H_CADON[0..15] 11




+1.2V_HT JCPUA
C7
HT LINK +VLDT_B 2 10U_0805_10V6K
D1
D2
VLDT_A0 VLDT_B0 AE2
AE3
1
< VLDT_A & VLDT_B : HyperTransport I/O ring power >
VLDT=500mA D3
VLDT_A1 VLDT_B1
AE4
VLDT_A2 VLDT_B2
D4 VLDT_A3 VLDT_B3 AE5

H_CADIP0 E3 AD1 H_CADOP0
H_CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0
E2 L0_CADIN_L0 L0_CADOUT_L0 AC1
H_CADIP1 E1 AC2 H_CADOP1
H_CADIN1 L0_CADIN_H1 L0_CADOUT_H1 H_CADON1
F1 L0_CADIN_L1 L0_CADOUT_L1 AC3
H_CADIP2 G3 AB1 H_CADOP2
H_CADIN2 L0_CADIN_H2 L0_CADOUT_H2 H_CADON2
G2 L0_CADIN_L2 L0_CADOUT_L2 AA1
H_CADIP3 G1 AA2 H_CADOP3
H_CADIN3 L0_CADIN_H3 L0_CADOUT_H3 H_CADON3
H1 L0_CADIN_L3 L0_CADOUT_L3 AA3
2 H_CADIP4 H_CADOP4 2
J1 L0_CADIN_H4 L0_CADOUT_H4 W2
H_CADIN4 K1 W3 H_CADON4
H_CADIP5 L0_CADIN_L4 L0_CADOUT_L4 H_CADOP5
L3 L0_CADIN_H5 L0_CADOUT_H5 V1
H_CADIN5 L2 U1 H_CADON5
H_CADIP6 L0_CADIN_L5 L0_CADOUT_L5 H_CADOP6
L1 L0_CADIN_H6 L0_CADOUT_H6 U2
H_CADIN6 M1 U3 H_CADON6
H_CADIP7 L0_CADIN_L6 L0_CADOUT_L6 H_CADOP7
N3 L0_CADIN_H7 L0_CADOUT_H7 T1
H_CADIN7 N2 R1 H_CADON7
H_CADIP8 L0_CADIN_L7 L0_CADOUT_L7 H_CADOP8
E5 L0_CADIN_H8 L0_CADOUT_H8 AD4
H_CADIN8 F5 AD3 H_CADON8
H_CADIP9 L0_CADIN_L8 L0_CADOUT_L8 H_CADOP9
F3 AD5
< From NB > H_CADIN9 F4
L0_CADIN_H9 L0_CADOUT_H9
AC5 H_CADON9 < To NB >
H_CADIP10 L0_CADIN_L9 L0_CADOUT_L9 H_CADOP10
G5 L0_CADIN_H10 L0_CADOUT_H10 AB4
H_CADIN10 H5 AB3 H_CADON10
H_CADIP11 L0_CADIN_L10 L0_CADOUT_L10 H_CADOP11
H3 L0_CADIN_H11 L0_CADOUT_H11 AB5
H_CADIN11 H4 AA5 H_CADON11
H_CADIP12 L0_CADIN_L11 L0_CADOUT_L11 H_CADOP12
K3 L0_CADIN_H12 L0_CADOUT_H12 Y5
H_CADIN12 K4 W5 H_CADON12
H_CADIP13 L0_CADIN_L12 L0_CADOUT_L12 H_CADOP13
L5 L0_CADIN_H13 L0_CADOUT_H13 V4
H_CADIN13 M5 V3 H_CADON13
H_CADIP14 L0_CADIN_L13 L0_CADOUT_L13 H_CADOP14
M3 L0_CADIN_H14 L0_CADOUT_H14 V5
H_CADIN14 M4 U5 H_CADON14
H_CADIP15 L0_CADIN_L14 L0_CADOUT_L14 H_CADOP15
N5 L0_CADIN_H15 L0_CADOUT_H15 T4
H_CADIN15 P5 T3 H_CADON15
L0_CADIN_L15 L0_CADOUT_L15

11 H_CLKIP0 J3 L0_CLKIN_H0 L0_CLKOUT_H0 Y1 H_CLKOP0 11
11 H_CLKIN0 J2 L0_CLKIN_L0 L0_CLKOUT_L0 W1 H_CLKON0 11
11 H_CLKIP1 J5 L0_CLKIN_H1 L0_CLKOUT_H1 Y4 H_CLKOP1 11
11 H_CLKIN1 K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 H_CLKON1 11

11 H_CTLIP0 N1 L0_CTLIN_H0 L0_CTLOUT_H0 R2 H_CTLOP0 11
11 H_CTLIN0 P1 L0_CTLIN_L0 L0_CTLOUT_L0 R3 H_CTLON0 11
3 3
11 H_CTLIP1 P3 L0_CTLIN_H1 L0_CTLOUT_H1 T5 H_CTLOP1 11
11 H_CTLIN1 P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 H_CTLON1 11

@ 6090022100G_B




< FAN Control Circuit : Vout = 1.6 x Vset >
+5VS


1A
1




D1
2 @
+FAN1 C183 1SS355_SOD323-2
JFAN +3VS
1
2




C192 10U_0805_10V4Z +FAN1 1
1 1