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Compal Confidential
2 2




QALEA/QALEB Schematics Document
AMD APU Trinity FS1r2 + FCH Hudson-M3 + GPU Seymour XTX/Thames XT

2012-01-16
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REV:0.4 3




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Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/04/18 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 16, 2012 Sheet 1 of 50
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Compal confidential
File Name : QALEA/QALEB
Themes XT M2/Seymour XTX M2

1
VRAM PCIE x 16 Gen2 1

64M16/128M16/256M16 Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2
DDR3 x 8 AMD FS1r2 APU Dual Channel
Page 17 24 BANK 0, 1, 2 Page 10 11
1.5V DDRIII 1600 (1866)
DP Port0 Trinity
LVDS uPGA 722 pin
translator DP Port2 35mm x 35mm
RTD2132S HDMI Conn.
Page 27
Page 25 DP Port1 Page 5 9

4 * x1 PCI-E 2.0 x4 UMI Gen. 1
LVDS Conn. 2.5GT/s per lane
Page 26 GPP3 GPP1 GPP0 2Channel Speaker
CardReader LAN
RTL 8111F
2 4 in 1 Conn. IC AZALIA Audio Codec Internal MIC 2

RTS5229 Hudson M3 CX20671-21Z
Page 29
uFCBGA-656 Audio Jacks
PCI Express USB(BT) 24.5mm x 24.5mm 14*USB2.0/
Combo jack
Mini card Slot 1 PCI-E(WLAN) 4*USB3.0,10*USB2.0
WLAN
FCH CRT (VGA DAC)
CMOS Camera Page 26
Page 33
CRT CONN
Page 28
Page 12 16
6*SATA serial BlueTooth CONN Page 32
USB PORT 3.0 x3 Page 34
SPI ROM LPC BUS USB PORT 2.0 x1 +Charger
4MB
Sub board WLAN Page 33
3
Page 35 Page 13
EC 3


ENE KB9012
Page 31 Finger Printer
Power Board 15" only G Sensor UPEK TCS5DA6C0
ST LIS34ALTR
Page 30
SATA0
ODD board SATA3.0 HDD CONN
LAN Track Point
Page 30

SATA1
Page 33 SATA ODD CONN
Int.KBD Page 30
Audio Jack+ Click Pad
Page 33

USB2.0 Page 33



FingerPrint Thermal Sensor
4 Fintek 5303 4

Page 32



Card reader Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/04/18 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 16, 2012 Sheet 2 of 50
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A B C D E




FCH Hudson-M2/3 Comal FCH Hudson-M2/3
Power Plane Description S0 S3 S5
SATA Port List PCIE Port List USB Port List
VIN Adapter power supply (19V) N/A N/A N/A
B+ AC or battery power rail for power circuit. N/A N/A N/A
USB1.1
SATA0 HDD PCIE0 LAN
+APU_CORE Core voltage for APU ON OFF OFF Port0 NC
SATA1 ODD PCIE1 WLAN




APU
+APU_CORE_NB Voltage for On-die VGA of APU ON OFF OFF
1
+1.5V 1.5V power rail for APU VDDIO and DDR ON ON OFF
Port1 NC 1
SATA2 NC PCIE2 NC
+0.75VS 0.75V switched power rail for DDR terminator ON OFF OFF USB2.0
+1.2VS 1.2V (VDDR, VDDP) switched power rail for APU ON OFF OFF
SATA3 NC PCIE3 Card Reader
+2.5VS 2.5V for APU VDDA ON OFF OFF
Port0 USB2.0 Port
SATA4 NC PCIE0 NC
+1.1VALW 1.1V switched power rail for FCH ON ON ON* Port1 NC
SATA5 NC PCIE1 NC




FCH
+1.1VS 1.1V switched power rail for FCH ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF
Port2 NC
PCIE2 NC
+VGA_CORE 0.95-1.2V switched power rail ON OFF OFF Port3 NC
+1.5VGS 1.5V switched power rail ON OFF OFF
PCIE3 NC
+1.8VGS 1.8V switched power rail ON OFF OFF
Port4 NC
+1.0VGS 1.0V switched power rail for VGA ON OFF OFF Port5 WLAN
+3VALW 3.3V always on power rail ON ON ON*
+3VS_WLAN 3.3V power rail for WLAN ON OFF OFF
Port6 CMOS
+3VS 3.3V switched power rail ON OFF OFF Port7 FP
+5VALW 5V always on power rail ON ON ON*
+5VS 5V switched power rail ON OFF OFF
Port8 BT
2 2
+VSB VSB always on power rail ON ON ON* Port9 NC
+RTCVCC RTC power ON ON ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Port10 USB 3.0
Port11 USB 3.0
Port12 USB 3.0
Port13 NC

Device Address HEX Device Address HEX
[email protected] : UMA only
[email protected] : DIS muxluss
Smart Battery 0001-011xb 15H F75303 (DDR,VRAM,CPUCORE)1001-101xb 9AH
[email protected] : PX4.0 Support
SB-TSI 1001-100xb 98H
[email protected] : PX5.0 Support
Seymour XTX 1000-0010b 82H [email protected] : USB camera
LVDS translator

[email protected] : ME components
[email protected], [email protected], [email protected] : VRAM

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[email protected]: Thames VGA
[email protected]: Seymour VGA




SDV:
[email protected]/[email protected]/[email protected]/[email protected] + [email protected]
(FCH_SMB0)


Device Address HEX PJ201,PJ401,PJ502,PJ503,PJ504,PJ601,PJ603,PJ604,
PJ701,PJ702,PJ703,PJ704,J1,J2301,J2401,J2402,J2403
DDR DIMM1 (FCH_SMB0) 1001-000xb PJ402,PJ403,PJ501,PJ602,PJ801,PJ802,PJ803,PJ804,PJ805
DDR DIMM2 (FCH_SMB0) 1001-001xb
WLAN (FCH_SMB0)
Security ROM




4 4




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/04/18 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 16, 2012 Sheet 3 of 50
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5 4 3 2 1




All the ASIC supplies, except for VDDR3, must fully reach their respective
nominal voltages within 20 ms of the start of the ramp-up sequence, though a
shorter ramp-up duration is preferred. There is no timing requirement on the
ramp up of VDDR3 relative to other power rails.
D D
The external pull-up resistors on the DDC/AUX signals (if applicable) should
ramp up before or after both VDDC and VDD_CT have ramped up.
VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC
should reach 90% before VDD_CT starts to ramp up (or vice versa).
For power down, reversing the ramp-up sequence is recommended.




C C




PE_GPIO0(PXS_RST#) PE_EN



BIF_VDDC

PE_GPIO1(PXS_PWREN)


PX_mode


B B
MOS




SI4800
LDO




Regulator
Regulator
T4+16clock

PWRGOOD




A A



Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/04/18 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 16, 2012 Sheet 4 of 50
5 4 3 2 1
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17 PCIE_CRX_GTX_P[0..15] PCIE_CTX_GRX_P[0..15] 17

17 PCIE_CRX_GTX_N[0..15] PCIE_CTX_GRX_N[0..15] 17


JCPU1A
PCI EXPRESS
PCIE_CRX_GTX_P0 AB8 AB2 PCIE_CTX_C_GRX_P0 C1 [email protected] 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P0
PCIE_CRX_GTX_N0 AB7 P_GFX_RXP0 P_GFX_TXP0 AB1 PCIE_CTX_C_GRX_N0 C2 [email protected] 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N0
PCIE_CRX_GTX_P1 AA9 P_GFX_RXN0 P_GFX_TXN0 AA3 PCIE_CTX_C_GRX_P1 C3 [email protected] 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P1
PCIE_CRX_GTX_N1 AA8 P_GFX_RXP1 P_GFX_TXP1 AA2 PCIE_CTX_C_GRX_N1 C4 [email protected] 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N1
PCIE_CRX_GTX_P2 AA5 P_GFX_RXN1 P_GFX_TXN1 Y5 PCIE_CTX_C_GRX_P2 C5 [email protected] 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P2
1 PCIE_CRX_GTX_N2 AA6 P_GFX_RXP2 P_GFX_TXP2 Y4 PCIE_CTX_C_GRX_N2 C6 [email protected] 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N2 1
PCIE_CRX_GTX_P3 Y8 P_GFX_RXN2 P_GFX_TXN2 Y2 PCIE_CTX_C_GRX_P3 C7 [email protected] 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P3
PCIE_CRX_GTX_N3 Y7 P_GFX_RXP3 P_GFX_TXP3 Y1 PCIE_CTX_C_GRX_N3 C8 [email protected] 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N3
PCIE_CRX_GTX_P4 W9 P_GFX_RXN3 P_GFX_TXN3 W3 PCIE_CTX_C_GRX_P4 C9 [email protected] 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P4
PCIE_CRX_GTX_N4 W8 P_GFX_RXP4 P_GFX_TXP4 W2 PCIE_CTX_C_GRX_N4 C10 [email protected] 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N4
PCIE_CRX_GTX_P5 W5 P_GFX_RXN4 P_GFX_TXN4 V5 PCIE_CTX_C_GRX_P5 C11 [email protected] 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P5
PCIE_CRX_GTX_N5 W6 P_GFX_RXP5 P_GFX_TXP5 V4 PCIE_CTX_C_GRX_N5 C12 [email protected] 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N5
PCIE_CRX_GTX_P6 V8 P_GFX_RXN5 P_GFX_TXN5 V2 PCIE_CTX_C_GRX_P6 C13 [email protected] 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P6
PCIE_CRX_GTX_N6 V7 P_GFX_RXP6 P_GFX_TXP6 V1 PCIE_CTX_C_GRX_N6 1 2 PCIE_CTX_GRX_N6




GRAPHICS
C14 [email protected] .1U_0402_16V7K
PCIE_CRX_GTX_P7 U9 P_GFX_RXN6 P_GFX_TXN6 U3 PCIE_CTX_C_GRX_P7 C15 [email protected] 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P7
PCIE_CRX_GTX_N7 U8 P_GFX_RXP7 P_GFX_TXP7 U2 PCIE_CTX_C_GRX_N7 C16 [email protected] 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N7
PCIE_CRX_GTX_P8 U5 P_GFX_RXN7 P_GFX_TXN7 T5 PCIE_CTX_C_GRX_P8 C17 [email protected] 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P8
PCIE_CRX_GTX_N8 U6 P_GFX_RXP8 P_GFX_TXP8 T4 PCIE_CTX_C_GRX_N8 C18 [email protected] 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N8
PCIE_CRX_GTX_P9 T8 P_GFX_RXN8 P_GFX_TXN8 T2 PCIE_CTX_C_GRX_P9 C19 [email protected] 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P9
PCIE_CRX_GTX_N9 T7 P_GFX_RXP9 P_GFX_TXP9 T1 PCIE_CTX_C_GRX_N9 C20 [email protected] 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N9
PCIE_CRX_GTX_P10 R9 P_GFX_RXN9 P_GFX_TXN9 R3 PCIE_CTX_C_GRX_P10 C21 [email protected] 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P10
PCIE_CRX_GTX_N10 R8 P_GFX_RXP10 P_GFX_TXP10 R2 PCIE_CTX_C_GRX_N10 C22 [email protected] 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N10
PCIE_CRX_GTX_P11 R5 P_GFX_RXN10 P_GFX_TXN10 P5 PCIE_CTX_C_GRX_P11 C23 [email protected] 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P11
PCIE_CRX_GTX_N11 R6 P_GFX_RXP11 P_GFX_TXP11 P4 PCIE_CTX_C_GRX_N11 C24 [email protected] 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N11
PCIE_CRX_GTX_P12 P8 P_GFX_RXN11 P_GFX_TXN11 P2 PCIE_CTX_C_GRX_P12 C25 [email protected] 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P12
PCIE_CRX_GTX_N12 P7 P_GFX_RXP12 P_GFX_TXP12 P1 PCIE_CTX_C_GRX_N12 C26 [email protected] 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N12
PCIE_CRX_GTX_P13 N9 P_GFX_RXN12 P_GFX_TXN12 N3 PCIE_CTX_C_GRX_P13 C27 [email protected] 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P13
PCIE_CRX_GTX_N13 N8 P_GFX_RXP13 P_GFX_TXP13 N2 PCIE_CTX_C_GRX_N13 C28 [email protected] 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N13
PCIE_CRX_GTX_P14 N5 P_GFX_RXN13 P_GFX_TXN13 M5 PCIE_CTX_C_GRX_P14 C29 [email protected] 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P14
PCIE_CRX_GTX_N14 N6 P_GFX_RXP14 P_GFX_TXP14 M4 PCIE_CTX_C_GRX_N14 C30 [email protected] 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N14
PCIE_CRX_GTX_P15 M8 P_GFX_RXN14 P_GFX_TXN14 M2 PCIE_CTX_C_GRX_P15 C31 [email protected] 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P15
PCIE_CRX_GTX_N15 M7 P_GFX_RXP15 P_GFX_TXP15 M1 PCIE_CTX_C_GRX_N15 C32 [email protected] 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N15
P_GFX_RXN15 P_GFX_TXN15
AE5 AD5 PCIE_CTX_C_DRX_P0 C33 1 2 .1U_0402_16V7K
35 PCIE_CRX_DTX_P0 P_GPP_RXP0 P_GPP_TXP0 PCIE_CTX_DRX_P0 35
AE6 AD4 PCIE_CTX_C_DRX_N0 C34 1 2 .1U_0402_16V7K
35 PCIE_CRX_DTX_N0 AD8 P_GPP_RXN0 P_GPP_TXN0 AD2 1 2 PCIE_CTX_DRX_N0 35
PCIE_CTX_C_DRX_P1 C123 .1U_0402_16V7K
33 PCIE_CRX_DTX_P1 P_GPP_RXP1 P_GPP_TXP1 PCIE_CTX_DRX_P1 33
AD7 AD1 PCIE_CTX_C_DRX_N1 C124 1 2 .1U_0402_16V7K
2 33 PCIE_CRX_DTX_N1 P_GPP_RXN1 P_GPP_TXN1 PCIE_CTX_DRX_N1 33 2
AC9 AC3
P_GPP_RXP2 P_GPP_TXP2
GPP
AC8 AC2
AC5 P_GPP_RXN2 P_GPP_TXN2 AB5 PCIE_CTX_C_DRX_P3 C35 1 2 .1U_0402_16V7K
35 PCIE_CRX_DTX_P3 AC6 P_GPP_RXP3 P_GPP_TXP3 AB4 1 2 .1U_0402_16V7K PCIE_CTX_DRX_P3 35
PCIE_CTX_C_DRX_N3 C36
35 PCIE_CRX_DTX_N3 P_GPP_RXN3 P_GPP_TXN3 PCIE_CTX_DRX_N3 35
AG8 AG2 UMI_TXP0_C C37 1 2 .1U_0402_16V7K
12 UMI_RXP0 P_UMI_RXP0 P_UMI_TXP0 UMI_TXP0 12
AG9 AG3 UMI_TXN0_C C38 1 2 .1U_0402_16V7K
12 UMI_RXN0 P_UMI_RXN0 P_UMI_TXN0 UMI_TXN0 12
AG6 AF4 UMI_TXP1_C C39 1 2 .1U_0402_16V7K
12 UMI_RXP1 AG5 P_UMI_RXP1 P_UMI_TXP1 AF5 1 2 UMI_TXP1 12
UMI_TXN1_C C40 .1U_0402_16V7K
12 UMI_RXN1 P_UMI_RXN1 P_UMI_TXN1 UMI_TXN1 12
AF7 AF1 UMI_TXP2_C C41 1 2 .1U_0402_16V7K
12 UMI_RXP2 P_UMI_RXP2 P_UMI_TXP2 UMI_TXP2 12
AF8 AF2 UMI_TXN2_C C42 1 2 .1U_0402_16V7K
12 UMI_RXN2 P_UMI_RXN2 P_UMI_TXN2 UMI_TXN2 12
AE8 AE2 UMI_TXP3_C C43 1 2 .1U_0402_16V7K
UMI




12 UMI_RXP3 P_UMI_RXP3 P_UMI_TXP3 UMI_TXP3 12
AE9 AE3 UMI_TXN3_C C44 1 2 .1U_0402_16V7K
12 UMI_RXN3 P_UMI_RXN3 P_UMI_TXN3 UMI_TXN3 12

+1.2VS 1 2 P_ZVDDP AG11 AH11 P_ZVSS 1 2
R1 196_0402_1% P_ZVDDP P_ZVSS R2 196_0402_1%

LOTES_ACA-ZIF-109-P12-A_FS1R2
[email protected]




3 3




4 4




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/04/18 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 16, 2012 Sheet 5 of 50
A B C D E
A B C D E




1 1



JCPU1B JCPU1C
MEMORY CHANNEL A MEMORY CHANNEL B
10 DDRA_SMA[15..0] U20 E13 DDRA_SDQ[63..0] 10 11 DDRB_SMA[15..0] T27 A14 DDRB_SDQ[63..0] 11
DDRA_SMA0 DDRA_SDQ0 DDRB_SMA0 DDRB_SDQ0
DDRA_SMA1 R20 MA_ADD0 MA_DATA0 J13 DDRA_SDQ1 DDRB_SMA1 P24 MB_ADD0 MB_DATA0 B14 DDRB_SDQ1
DDRA_SMA2 R21 MA_ADD1 MA_DATA1 H15 DDRA_SDQ2 DDRB_SMA2 P25 MB_ADD1 MB_DATA1 D16 DDRB_SDQ2
DDRA_SMA3 P22 MA_ADD2 MA_DATA2 J15 DDRA_SDQ3 DDRB_SMA3 N27 MB_ADD2 MB_DATA2 E16 DDRB_SDQ3
DDRA_SMA4 P21 MA_ADD3 MA_DATA3 H13 DDRA_SDQ4 DDRB_SMA4 N26 MB_ADD3 MB_DATA3 B13 DDRB_SDQ4
DDRA_SMA5 N24 MA_ADD4 MA_DATA4 F13 DDRA_SDQ5 DDRB_SMA5 M28 MB_ADD4 MB_DATA4 C13 DDRB_SDQ5
DDRA_SMA6 N23 MA_ADD5 MA_DATA5 F15 DDRA_SDQ6 DDRB_SMA6 M27 MB_ADD5 MB_DATA5 B16 DDRB_SDQ6
DDRA_SMA7 N20 MA_ADD6 MA_DATA6 E15 DDRA_SDQ7 DDRB_SMA7 M24 MB_ADD6 MB_DATA6 A16 DDRB_SDQ7
DDRA_SMA8 N21 MA_ADD7 MA_DATA7 DDRB_SMA8 M25 MB_ADD7 MB_DATA7
DDRA_SMA9 M21 MA_ADD8 H17 DDRA_SDQ8 DDRB_SMA9 L26 MB_ADD8 C17 DDRB_SDQ8
DDRA_SMA10 U23 MA_ADD9 MA_DATA8 F17 DDRA_SDQ9 DDRB_SMA10 U26 MB_ADD9 MB_DATA8 B18 DDRB_SDQ9
DDRA_SMA11 M22 MA_ADD10 MA_DATA9 E19 DDRA_SDQ10 DDRB_SMA11 L27 MB_ADD10 MB_DATA9 B20 DDRB_SDQ10
DDRA_SMA12 L24 MA_ADD11 MA_DATA10 J19 DDRA_SDQ11 DDRB_SMA12 K27 MB_ADD11 MB_DATA10 A20 DDRB_SDQ11
DDRA_SMA13 AA25 MA_ADD12 MA_DATA11 G16 DDRA_SDQ12 DDRB_SMA13 W26 MB_ADD12 MB_DATA11 E17 DDRB_SDQ12
DDRA_SMA14 L21 MA_ADD13 MA_DATA12 H16 DDRA_SDQ13 DDRB_SMA14 K25 MB_ADD13 MB_DATA12 B17 DDRB_SDQ13
DDRA_SMA15 L20 MA_ADD14 MA_DATA13 H19 DDRA_SDQ14 DDRB_SMA15 K24 MB_ADD14 MB_DATA13 B19 DDRB_SDQ14
MA_ADD15 MA_DATA14 F19 DDRA_SDQ15 MB_ADD15 MB_DATA14 C19 DDRB_SDQ15
DDRA_SBS0# U24 MA_DATA15 DDRB_SBS0# U27 MB_DATA15
10 DDRA_SBS0# MA_BANK0 11 DDRB_SBS0# MB_BANK0
DDRA_SBS1# U21 H20 DDRA_SDQ16 DDRB_SBS1# T28 C21 DDRB_SDQ16
10 DDRA_SBS1# MA_BANK1 MA_DATA16 11 DDRB_SBS1# MB_BANK1 MB_DATA16
DDRA_SBS2# L23 F21 DDRA_SDQ17 DDRB_SBS2# K28 B22 DDRB_SDQ17
10 DDRA_SBS2# MA_BANK2 MA_DATA17 J23 11 DDRB_SBS2# MB_BANK2 MB_DATA17 C23
DDRA_SDQ18 DDRB_SDQ18
10 DDRA_SDM[7..0] MA_DATA18 11 DDRB_SDM[7..0] MB_DATA18
DDRA_SDM0 E14 H23 DDRA_SDQ19 DDRB_SDM0 D14 A24 DDRB_SDQ19
DDRA_SDM1 J17 MA_DM0 MA_DATA19 G20 DDRA_SDQ20 DDRB_SDM1 A18 MB_DM0 MB_DATA19 D20 DDRB_SDQ20
DDRA_SDM2 E21 MA_DM1 MA_DATA20 E20 DDRA_SDQ21 DDRB_SDM2 A22 MB_DM1 MB_DATA20 B21 DDRB_SDQ21
DDRA_SDM3 F25 MA_DM2 MA_DATA21 G22 DDRA_SDQ22 DDRB_SDM3 C25 MB_DM2 MB_DATA21 E23 DDRB_SDQ22
DDRA_SDM4 AD27 MA_DM3 MA_DATA22 H22 DDRA_SDQ23 DDRB_SDM4 AF25 MB_DM3 MB_DATA22 B23 DDRB_SDQ23
DDRA_SDM5 AC23 MA_DM4 MA_DATA23 DDRB_SDM5 AG22 MB_DM4