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5 4 3 2 1
Amazon LCD PC Block Diagram 1
VID[0:6]
D
CHA/B AMD AM2 CPU VCORE D
DDRII X2 uPGA940 page:34
page:8 VCORE:+1.196 ~ +0.748
VCCP:+1.1V
VCCA:+1.8V or +1.5V
+/- CPU_CLK
page:4-7
18.5" panel Clock Gengerator
page:19 +/- HCLK
page:3
HT-LINK
LVDS LVDS
C
MXM
MODULE PCIEX16
RS780MN C
HOST
(MXM3.0) page:20
LVDS, DMI, DDR CLK
POWER
10/100 PCI-E GND PCI-E/USB
Ethernet
PCI-E page:10-13 MINI CARD WLAN
RJ-45
page:25
RTL8103EL A_LINK
page:30
Module
page:24
SATA HDD, ODD
6 in 1 Card Reader SB700 page:28
Bluetooth
B
page:27 JR385
page:27 USB
B
RTC, AC97, SATA, IDE, LPC, CPU RESERVE
PCI-E, USB, DMI, PCI
SMB, GPIO, CLK
USB Camera Conn. Camera
page:22 Module
SPK HDA CODEC
page:29 Azalia
ALC269 page:14-18
USB USB PORT X4
LINE OUT
page:23
page:29
Rear page:26
USB LPC BUS
USB X2
A H/P OUT EC A
page:29 side USB SPI
page:26
ITE8512 Quanta Computer Inc.
page:32 Flash
Int. Mic
page:29
page:32 Size Document Number
PROJECT : ZN1
Rev
B
Block Diagram
Date: Friday, May 08, 2009 Sheet 1 of 41
5 4 3 2 1
5 4 3 2 1
2
Voltage Rails
LAYER 1 : TOP Power On Sequence
LAYER 2 : VCC Power Voltage S0~S2 S3 S4 S5 Ctl Signal
LAYER 3 : IN1 15VPCU 15V V V V V
D
LAYER 4 : IN2 5VPCU 5V V V V V VIN From AC IN D
LAYER 5 : GND 3VPCU 3V V V V V VIN 5VPCU 3VPCU
LAYER 6 : BOT RVCC3 3V V V V V RVCC_ON From PWM SYS_HWPG(PCU)
RVCC1.2 1.2V V V V V RVCC_ON
From Power Button NBSWON#
5VSUS 5V V V SUSD From EC RVCC_ON
1.8VSUS 1.8V V V SUSON RVCC5
VCC5 5V V MAIND
VCC3 3V V MAIND RVCC3
VCC1.8 1.8V V MAIND
VCC1.5 1.5V V MAINON RVCC1.2 >10ms
VCC1.2 1.2V V MAINON From EC RSMRST#
CPU_VDDA 2.5V V VCC3
>100ms
NB_CORE 1.2V V VRON From EC DNBSWON#
SMDDR_VTERM 0.9V V SUSON From SB PCIE_WAKE#
CPU_CORE By CPU V VR_ON
From SB to EC SUSB#,SUSC# SUSON
C From EC SUSON C
3VSUS 1.8VSUS SMDDR_VREF SMDDR_VTERM
From PWM HWPG_1.8V (SUS) MAINON
From EC MAINON
VCC5 VCC3 VCC2.5 VCC1.8 VCC1.5 NB_CORE 1.1V_NB
From PWM HWPG_1.5V,HWPG_2.5V,GFXPG(MAIN) HWPG_1.2_NB
From EC VRON
CPU_CORE0, CPU_CORE1, CPU VDDNB_CORE, VCC1.2
From PWM VRM_PWRGD (CPU)
HWPG
From EC ECPWROK
SB_PWRGD 0ns~30ns
B
NB_PWRGD 99ms~108ms B
From SB CPU_PWRGD/LDT_PG
From SB PLTRST# PCIRST#
From SB CPU_LDT_RST#
T1 T2 T3
From SB CPU_LDT_STOP#
T1>= 70 ms 1ms < T2 < 10ms
1ms < T3 < 5ms
A A
Quanta Computer Inc.
PROJECT : ZN1
Size Document Number Rev
B
SYSTEM INFORMATION
Date: Friday, May 08, 2009 Sheet 2 of 41
5 4 3 2 1
5 4 3 2 1
CLK_GEN_SLG8SP628
VCC3 CLK_VDD CLK_VDDIO
L26 L28
VCC1.2
BK1608HS600 BK1608HS600
C260 C258 C270 C275 C269 C268 C276 C273 C274 C262 C278 C257 C277 C267
C252 C272
22U/6.3V_8 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 22U/6.3V_8 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4
D D
Clock chip has internal serial terminations
for differencial pairs, external resistors are
reserved for debug purpose.
Place within 0.5"
of CLKGEN
U12 R182
*261/F_4
4 50 CPUCLKP_R RP7 1 2 0X2 CPUCLKP
VCC3 CLK_VDD_USB CLK_VDD 16
VDDDOT
VDDSRC
CPUK8_0T
CPUK8_0C
49 CPUCLKN_R 3 4 CPUCLKN CPUCLKP
CPUCLKN
6
6
To CPU 200 Mhz
L27 26
VDDATIG
35
BK1608HS600 VDDSB_SRC NBGFX_CLKP_R RP4
40 30 1 2 0X2 NBGFX_CLKP
NBGFX_CLKP 12
C263 C250 VDDSATA ATIG0T NBGFX_CLKN_R NBGFX_CLKN To NB
48
VDDCPU ATIG0C
29 3 4 NBGFX_CLKN 12 RS780 for VGA
C256 22U/6.3V_8 55 28 T83
0.1u/10V_4 10uF_0805 VDDHTT ATIG1T
56 27 T82
VDDREF ATIG1C
63
VDD48
2
37 SBLINK_CLKP_R RP9 1 2 0X2 SBLINK_CLKP
C C255 SB_SRC0T SBLINK_CLKN_R SBLINK_CLKN SBLINK_CLKP 12 To NB C
11 36 3 4
2.2U_0805 CLK_VDDIO 17
VDDSRC_IO0 SB_SRC0C
32 SBSRC_CLKP_R 1 2 0X2 SBSRC_CLKP SBLINK_CLKN 12 100 Mhz
1
VDDSRC_IO1 SB_SRC1T SBSRC_CLKN_R RP6 SBSRC_CLKN SBSRC_CLKP 14 To SB
25 31 3 4 SBSRC_CLKN 14
VDDATIG_IO SB_SRC1C
34
VDDSB_SRC_IO
47
VDDCPU_IO
22 T81
SRC0T
21 T77
SRC0C
1 20 T79
GND48 SRC1T
7 19 T78
GNDDOT SRC1C CLK_PCIE_MINI_R RP3
10 15 1 2 0X2 CLK_PCIE_WLAN
CLK_PCIE_WLAN 30
GNDSRC0 SRC2T CLK_PCIE_MINI#_R CLK_PCIE_WLAN# To Mini PCIE Slot(WLAN)
18 14 3 4 CLK_PCIE_WLAN# 30
GNDSRC1 SRC2C CLK_PCIE_MXM_R RP2
24 QFN64 13 1 2 0X2 CLK_MXM
CLK_MXM 20
GNDATIG SRC3T CLK_PCIE_MXM#_R CLK_MXM# To MXM MODULE
33 12 3 4
C266 33P CG_XIN 43
GNDSB_SRC
GNDSATA
SRC3C
SRC4T
9 CLK_PCIE_LAN_R RP1 1 2 0X2 CLK_PCIE_LAN CLK_MXM# 20
CLK_PCIE_LAN 24
100 Mhz
46 8 CLK_PCIE_LAN#_R 3 4 CLK_PCIE_LAN# To LAN Controller
2
GNDCPU SRC4C CLK_PCIE_LAN# 24
52
Y2 GNDHTT
60
GNDREF CLK_PCIE_JM385_R RP8
14.318MHZ/20P 42 1 2 0X2 CLK_PCIE_JM385
CLK_PCIE_JM385 27
SRC6T/SATAT CLK_PCIE_JM385#_R CLK_PCIE_JM385# To 6 in 1 Controller
41 3 4
1
CG_XOUT CG_XIN SRC6C/SATAC CLK_PCIE_JM385# 27
61 6 T76
C264 33P CG_XOUT X1 SRC7T/27M_SS
62 5 T75
X2 SRC7C/27M_NS
2 54 NBHT_REFCLKP_R RP5 1 2 0X2 NBHT_REFCLKP
8,15,19,30 PCLK_SMB
8,15,19,30 PDAT_SMB 3
SMBCLK
SMBDAT
HTT0T/66M
HTT0C/66M
53 NBHT_REFCLKN_R 3 4 NBHT_REFCLKN NBHT_REFCLKP
NBHT_REFCLKN
12
12
To NB HT BUS 100 Mhz
CLK_PD# 51 64 CLK_48M_USB_R R177 33_4 CLK_48M_USB
CLK_VDD PD# 48MHz_0 CLK_48M_USB 15
To SB USB
48 Mhz
T80 23 59 SEL_HTT66
R315 8.2K_4 CLK_PD# CLKREQ0# REF0/SEL_HTT66 SEL_SATA
B
45
CLKREQ1# REF1/SEL_SATA
58 Ra B
T85 CLKREQ2# 44 57 SEL_27 R180 158/F_4 EXT_NB_OSC To NB
CLKREQ2# REF2/SEL_27 R181 90.9/F_4 EXT_NB_OSC 12
T84 39
CLKREQ3#
38
CLKREQ4#
Rb CLOCK INPUT TABLE
TGND0
TGND1
TGND2
TGND3
TGND4
TGND5
TGND6
TGND7
TGND8
TGND9
C265 C259 CLOCKS RS780
*10p/50V_4 *10p/50V_4
SLG8SP628 HT_REFCLKP 100M DIFF
65
66
67
68
69
70
71
72
73
74
HT_REFCLKN 100M DIFF
REFCLK_P 14M SE (1.1V)
REFCLK_N vref
GFX_REFCLK 100M DIFF(IN/OUT)*
GPP_REFCLK NC or 100M DIFF OUTPUT
GPPSB_REFCLK 100M DIFF
CLK_VDD
R327
*8.2K_4
SEL_SATA
SEL_HTT66
A SEL_27 A
1 66 MHz 3.3V single ended HTT clock
SEL_HTT66
R326 R328 R316 0* 100 MHz differential HTT clock
8.2K_4 8.2K_4 8.2K_4
1* 100 MHz non-spreading differential SRC clock
SEL_SATA
0 100 MHz spreading differential SRC clock
Quanta Computer Inc.
1 27MHz and 27M SS outputs
SEL_27
0* 100 MHz SRC clock PROJECT : ZN1
Size Document Number Rev
* default 1A
Clock Generator
Date: Friday, May 08, 2009 Sheet 3 of 41
5 4 3 2 1
5 4 3 2 1
4
CPU HyperTransport Interface
D
VDDLDTRUNCPU is connected to the VDD_LDT_RUN power D
supply through the package or on the die. It is only connected
on the board to decoupling near the CPU package.
VCC1.2 VLDT_RUN VLDT_RUN
U9A
R98 *short0805 C149
AJ4 VLDT_06 VLDT_08 H6
AJ3 VLDT_05 VLDT_07 H5
R100 *short0805 AJ2 H2
VLDT_02 VLDT_04
AJ1 VLDT_01 VLDT_03 H1
4.7U_0603
10 HT_CADIN15_P U6 L0_CADIN_H15 L0_CADOUT_H15 Y5 HT_CADOUT15_P 10
10 HT_CADIN15_N V6 L0_CADIN_L15 L0_CADOUT_L15 Y4 HT_CADOUT15_N 10
10 HT_CADIN14_P T4 L0_CADIN_H14 L0_CADOUT_H14 AB6 HT_CADOUT14_P 10
10 HT_CADIN14_N T5 L0_CADIN_L14 L0_CADOUT_L14 AA6 HT_CADOUT14_N 10
10 HT_CADIN13_P R6 L0_CADIN_H13 L0_CADOUT_H13 AB5 HT_CADOUT13_P 10
10 HT_CADIN13_N T6 L0_CADIN_L13 L0_CADOUT_L13 AB4 HT_CADOUT13_N 10
10 HT_CADIN12_P P4 L0_CADIN_H12 L0_CADOUT_H12 AD6 HT_CADOUT12_P 10
10 HT_CADIN12_N P5 L0_CADIN_L12 L0_CADOUT_L12 AC6 HT_CADOUT12_N 10
10 HT_CADIN11_P M4 L0_CADIN_H11 L0_CADOUT_H11 AF6 HT_CADOUT11_P 10
10 HT_CADIN11_N M5 L0_CADIN_L11 L0_CADOUT_L11 AE6 HT_CADOUT11_N 10
10 HT_CADIN10_P L6 L0_CADIN_H10 L0_CADOUT_H10 AF5 HT_CADOUT10_P 10
10 HT_CADIN10_N M6 L0_CADIN_L10 L0_CADOUT_L10 AF4 HT_CADOUT10_N 10
10 HT_CADIN9_P K4 L0_CADIN_H9 L0_CADOUT_H9 AH6 HT_CADOUT9_P 10
10 HT_CADIN9_N K5 L0_CADIN_L9 L0_CADOUT_L9 AG6 HT_CADOUT9_N 10
10 HT_CADIN8_P J6 L0_CADIN_H8 L0_CADOUT_H8 AH5 HT_CADOUT8_P 10
C 10 HT_CADIN8_N K6 L0_CADIN_L8 L0_CADOUT_L8 AH