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8 7 6 5 4 3 2 1
Version 1.0
Cover Sheet
Block Diagram
1
2
MS-6530 06/27/2001 Update
INTEL (R) Brookdale Chipset
GPIO Spec. 3
D
Willamette/Northwood 478pin mPGA-B Processor Schematics D
Clock Generation 4
CPU:
mPGA478-B INTEL CPU Sockets 5-6
Willamette/Northwood mPGA-478B Processor
INTEL Brookdale MCH -- North Bridge 7-8
INTEL ICH2 -- South Bridge 9 - 10 System Brookdale Chipset:
INTEL MCH (North Bridge) +
LPC I/O W83627HF 11
INTEL ICH2 (South Bridge)
AC'97 Codec 12
On Board Chipset:
Audio Amp TL072 13
C BIOS -- FWH C
FWH -- BIOS 14
AC'97 Codec -- AD1881/1885
SDR DIMM-168 15 LPC Super I/O -- W83627HF
AGP 4X SLOT (1.5V) 16 Clock Generation -- CY28324
/ICS950208
PCI SLOT 1 & 2 & 3 17
LAN -- INTEL 82562ET/EM
IDE CONNECTORS 18
Front Panel & Connectors 19
USB & FAN Connectors 20
B
Game Port and CPU Thermal-strip 21 Expansion Slots: B
AGP2.0 SLOT * 1
Votlage Regulator 22
PCI2.2 SLOT *3
Intersil HIP6301 PWM 23 CNR SLOT *0
IO Connectors 24 ISA SLOT * 1 (Share PCI3)
LAN INTEL 82562EM/ET 25
Option :
PCI TO ISA BRIDGE AND ISA SLOT 26,27
A -> Without LAN
JUMPER SETTING 28 T -> Support CPU Thermstrip Function
A A
MANUAL 29
Title Rev
Design Guide 30,31,32 M i c ro-Star MS-6530 100
Document Number
HISTORY 1 33 Cover Sheet
Last Revision Date:
Wednesday, July 04, 2001 Sheet 1 of 33
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
(478PINS)
(100MHz)
Power
Supply VRM Willamette/Northwood CK408 Clock
CONN 9.X Socket (mPGA478-B) (100MHz)
(400MHz) Scalable Bus Scalable Bus/2
4 X (66MHz) AGP
AGP 4X
(1.5V) MCH: Memory
Controller HUB
( 5 93PINS/FCBGA) (133MHz)
DIMM 1:2
VRM
AGP
CONN
( 66MHz X 4 ) HUB Interface
(14.318MHz)
C Hardware SM Bus C
Monitor ICH2: I/O PCI (33MHz)
PCI Slots 1:3
( 3 60PINS/EBGA)
Controller HUB
IDE CONN 1&2
(48MHz)
PCI TO ISA BRIDGE ISA SLOT 1
(33MHz)
(33MHz)
LPC Bus AC Link
USB Port 0:3
AC '97 Audio
FWH: Firmware HUB AMP
Codec
SIO
Line Out
MIC In
B
Audio In B
LAN
Modem-In
PS2 Mouse & Parallel (1) Floppy Disk Stuffing
Options CD-ROM
Keyboard Serial (2) Drive CONN
RJ45
A A
Title Rev
M i c ro-Star MS-6530 100
Document Number
Block Diagram
Last Revision Date:
Wednesday, July 04, 2001 Sheet 2 of 33
8 7 6 5 4 3 2 1
5 4 3 2 1
General Purpose I/O Spec.
FWH
ICH2
GPIO Pin PIN # Type Function
GPIO Pin PIN # Type Function
D GPI 0 6 I ATA IDE 1 Detect D
GPIO 0 M3 I PCI TO ISA REQA#
GPI 1 5 I ATA IDE 2 Detect
GPIO 1 L3 I Not Using (PREQ#5)
GPI 2 4 I Not Using
GPIO 2 N3 I Not Using (INTE#)
GPI 3 3 I Not Using
GPIO 3 N2 I Not Using (INTF#)
GPIO 4 N1 I Not Using (INTG#)
SIO
GPIO 5 M4 I Not Using (INTH#)
GPIO Pin PIN # Type Function
GPIO 6 Y11 I R e served for futuer
GP32 71 I/OD Non Connect
GPIO 7 AA11 I Non Connect
GP24 89 I/OD Non Connect
GPIO 8 Y14 I LAN Wake Up
GP34 69 I/OD Non Connect
C
GPIO 9 Y22 I AC'97 Serial Data In 0 C
GP33 70 I/OD Non Connect
GPIO 10 I Non Connect
GPIO 11 AB17 I Not Using (SMB_ALERT)
GPIO 12 W14 I External SMI
GPIO 13 AB15 I LPC PME
GPIO 14~15 I Not Implemented DEVICE ICH INT Pin IDSEL
GPIO 16 L2 O PCI TO ISA GNTA#
PCI Slot 1 INTA# AD16
GPIO 17 L4 O Non Connect INTB#
INTC#
GPIO 18 A15 O Non Connect
INTD#
B
GPIO 19 D14 O Non Connect B
PCI Slot 2 INTB# AD17
GPIO 20 C14 O Non Connect
INTC#
GPIO 21 L1 O PCI TO ISA NOGO INTD#
INTA#
GPIO 22 B14 OD Non Connect
GPIO 23 A14 O BIOS Locked/Unlocked PCI Slot 3 INTC# AD18
INTD#
GPIO 24 V21 O R e served for futuer
INTA#
GPIO 25 W15 O LAN Enable/Disable Detected INTB#
GPIO 26 O Non Connect
ISA SLOT AD22
GPIO 27 AB14 I/O Non Connect
GPIO 28 AA14 I/O LAN ENABLE/DISABLE
GPIO 29~31 I/O Not Implemented
A A
Title Rev
M i c ro-Star MS-6530 100
Document Number
GPIO Spec.
Last Revision Date:
Wednesday, July 04, 2001 Sheet 3 of 33
5 4 3 2 1
8 7 6 5 4 3 2 1
Put under Bead
*Trace less 0.5"
CP5 CLOCK GENERATOR BLOCK Shut Source Termination Resistors Pull-Down Capacitors
2 1
CPUCLK R230 49.9RST
U18 CPUCLK# R231 49.9RST CN14 X_10p
FB21 X_601S/0805 39 41 R243 33RST CPUCLK MCHCLK R232 49.9RST CPUCLK 8 7
VCC3 CPU_VDD CPU0 CPUCLK 5
40 R238 33RST CPUCLK# MCHCLK# R233 49.9RST CPUCLK# 6 5
+
CB160 CPU0# CPUCLK# 5
CT33 CB159 CB169 MCHCLK 4 3
104P Rubycon 105P/0805 104P 36 38 R239 33RST MCHCLK MCHCLK# 2 1
CPU_GND CPU1 37 R240 33RST MCHCLK# MCHCLK 7
CPU1# MCHCLK# 7
D ELS10/16-B D
46 C_STP C160 X_10p
for good filtering from 10K~1M MREF_VDD 45 C_STP P_STP C161 X_10p
CB168 3VMREF/CPU_STP# 44 P_STP Trace less 0.2"
104P 43 3VMREF#/PCI_STP# CN15 X_10p
MREF_GND 49.9ohm for 50ohm M/B impedance
Put under Bead RN16 8P4R-33 MCH_66 8 7
32 31 1 2 MCH_66
MCH_66 7
ICH_66 6 5
CP6 3V66_VDD 3V66_0 30 3 4 ICH_66 AGPCLK 4 3
3V66_1 ICH_66 10
2 1 CB171 28 5 6 AGPCLK 3V66_4 2 1
R227 104P 29
3V66_GND
3V66_2
3V66_3
27 3V66_3 7 8 3V66_4 AGPCLK 16 CLOCK STRAPPING RESISTORS
X_0/0805
6 FS2 7 8 ICH_PCLK
ICH_PCLK 9
FS4 R315 10K VCC3V
FB27 X_601S/0805 VCC3V 9 FS2/PCI_F0 7 FS3 5 6 FWH_PCLK FS3 R318 10K VCC3V
VCC3 PCI_VDD FS3/PCI_F1 8 MODE 3 4 SIO_PCLK FWH_PCLK 14 ICH_PCLK C258 X_10P
+
MODE/PCI_F2 SIO_PCLK 11
CB204 CT37 CB196 CB198 1 2 FS1 R298 X_10K VCC3V FWH_PCLK C259 X_10P
104P Rubycon 105P/0805 104P 5 10 FS4 R299 10K SIO_PCLK C260 X_10P
PCI_GND FS4/PCI0 11 RN21 8P4R-33
ELS10/16-B PCI1 ISAPCLK FS0 R303 10K VCC3V CN17 X_10p
18 12 7 8 ISAPCLK 26
PCI_VDD PCI2 14 5 6 PCICLK0 R308 X_10K PCICLK2 8 7
for good filtering from 10K~1M CB194 PCI3 15 3 4 PCICLK1 PCICLK0 17 PCICLK1 6 5
104P 13 PCI4 PCICLK2 PCICLK1 17 PCICLK0
16 1 2 PCICLK2 17 4 3
PCI_GND PCI5 17 R316 10K VCC3V ISAPCLK 2 1
*Put GND copper under Clock Gen. PCI6 RN22 8P4R-33 FS2 R317 X_10K
connect to every GND pin 24
48_VDD 22 FS0 R313 33 ICH_48
* 40 mils Trace on Layer 4 FS0/48MHz ICH_48 10
CB199 23 FS1 R307 33 SIO_48 MODE R314 X_10K
with GND copper around it 104P 21 FS1/24_48MHz SIO_48 11 ICH_48 C193 10P
48_GND SIO_48 C187 10P
* put close to every power pin 2 R249 33 ICH_14
C ICH_14 10 C
REF_VDD 48 MUL0 R289 33 OSC MUL0 R273 X_10K VCC3V
* Trace Width 7mils. VCC3 CB197 MUL0/REF0
1 MUL1 OSC 27 R274 10K
104P 47 MUL1/REF1 R465 X_33 CODE_14
* Same Group spacing 15mils REF_GND CODE_14 12 MUL1 R300 10K VCC3V OSC C182 10P
34 3 C179 22p R301 X_10K ICH_14 C167 10P
* Different Group spacing 30mils CORE_VDD X1 32pF CODE_14 C257 X_10P
R312 CB170 X3 14M-32pf-HC49S-D
* Different mode spacing 7mils on itself 10K 104P 33 4 C175 22p CRST# R246 10K VCC3V
CORE_GND X2
SMBCLK 26 35 R226 475RST
10,11,15 SMBCLK SMBDATA 25 SCLK IREF SMBCLK R264 1K
10,11,15 SMBDATA SDATA 20 CRST# R248 X_0 CLK_RST# SMBDATA R263 1K VCC3 used only for EMI issue
RST# CLK_RST# 19
R311 0 19 42 R225 4.7K VCC3V
VCC3V
VTT_GD# PWR_DN#
R327 220 Q32 ICS950208/CY283234 C_STP R224 1K VCC3V
Trace less 0.2"
VCCP
2N3904S P_STP R219 1K
R324 X_1K For Cypress
28324
RESET BLOCK
B B
R360 330 VCC3
R367 330 VCC3 PCIRST# 3 4
PCIRST# PCIRST#2 11,16,17
9 PCIRST# 1 2 PCIRST#1 7 U24B
U24A DM7407-SOIC14
DM7407-SOIC14 C230 (VCC5_SB)
(VCC5_SB)
X_10P
R330 X_1K S u p p o rt Power-Off CD-IN Player Function :
VCC5 E n a b le -> Install R329 , Not R330
R329 1K VCC5_SB
D i s a ble -> Install R330 , Not R329
VCC3
R356 HD_RST#
HD_RST# 18
4.7K
R333 4.7K Q34
2N3904S
A A
PCIRST# R355 4.7K Q39
2N3904S
R354 Title Rev
10K M i c ro-Star MS-6530 100
Document Number
Clock CY28323/4
Last Revision Date:
Wednesday, July 04, 2001 Sheet 4 of 33
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU SIGNAL BLOCK
VCCPS+ 23
7 HA#[3..31] VCCPS- 23
VID[0..4] 11,23
HA#28
HA#18
1
0
9
7
6
5
4
3
2
1
0
9
7
6
5
4
3
2
1
0
HA#3
HA#3
HA#2
HA#2
HA#2
HA#2
HA#2
HA#2
HA#2
HA#2
HA#2
HA#1
HA#1
HA#1
HA#1
HA#1
HA#1
HA#1
HA#1
HA#1
HA#9
HA#7
HA#6
HA#5
HA#4
HA#3
HA#8
VID2
VID0
VID4
VID3
VID1
AD26
AC26
AE25
D D
AB1
AE1
AE2
AE3
AE4
AE5
W2
W1
M1
M4
M3
M6
T5
T4
T2
T1
U4
R6
U3
U1
R3
R2
N5
N4
N2
N1
Y1
V3
V2
P6
P4
P3
K1
K4
K2
A5
A4
L2
L3
L6
U4A
A35#
A34#
A33#
A32#
A31#
A30#
A29#
A28#
A27#
A26#
A25#
A24#
A23#
A22#
A21#
A20#
A19#
A18#
A17#
A16#
A15#
A14#
A13#
A12#
A11#
A10#
DBR#
A9#
A8#
A7#
A6#
A5#
A4#
A3#
VCC_SENSE
VID4#
VID3#
VID2#
VID1#
VID0#
VSS_SENSE
ITP_CLK1
ITP_CLK0
7 HDBI#[0..3] HDBI#0 E21
HDBI#1 G25 DBI0# AA21 GTLREF1
HDBI#2 P26 DBI1# GTLREF3 AA6 GTLREF2
HDBI#3 V21 DBI2# GTLREF2 F20
DBI3# GTLREF1 F6
AC3 GTLREF0 CPU GTL REFERNCE VOLTAGE BLOCK
V6 IERR# AB4 BPM#5
B6 MCERR# BPM5# AA5 BPM#4 VCCP
9 FERR# Y4 FERR# BPM4# Y6
9 STPCLK# AA3 STPCLK# BPM3# AC4
HINIT# W5 BINIT# BPM2# AB5 BPM#1 R73
9 HINIT# AB2 INIT# BPM1# AC6 BPM#0 2/3*Vccp 49.9RST
RSP# BPM0# GTLREF1
7 HDBSY# H5 H3 HREQ#4 HREQ#[0..4] 7
H2 DBSY# REQ4# J3 HREQ#3 C42 C41 C51 R72
7 HDRDY# J6 DRDY# REQ3# J4 HREQ#2 220p 220p 105P/0805 100RST
7 HTRDY# TRDY# REQ2# K5 HREQ#1
G1 REQ1# J1 HREQ#0
7 HADS# G4 ADS# REQ0#
7 HLOCK# G2 LOCK# AD25
7 HBNR# BNR# TESTHI12
7 HIT# F3 A6 R69 4.7K
E3 HIT# TESTHI11 Y3
7 HITM# D2 HITM# TESTHI10 W4 R31 4.7K VCCP
7 HBPRI# E2 BPRI# TESTHI9 U6
C 7 HDEFER# C
DEFER# TESTHI8 AB22
ITP_TDI C1 TESTHI7 AA20 R35
D5 TDI TESTHI6 AC23 R70 4.7K 2/3*Vccp 49.9RST
F7 TDO TESTHI5 AC24 GTLREF2
ITP_TRST# E6 TMS TESTHI4 AC20
Trace : 10 mil width 10mil space D4 TRST# TESTHI3 AC21 C34 C33 C13 R34
B3 TCK TESTHI2 AA2 R36 4.7K 220p 220p 105P/0805 100RST
11 CPU_TMPA C4 THERMDA TESTHI1 AD24 VCCP
11 VTIN_GND THERMTRIP# A2 THERMDC TESTHI0
AF26 THERMTRIP# AF23
21 THERMTRIP# C3