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A B C D E

BATTERY CHARGER
Hawke Intel Discrete Block Diagram INPUTS
MAX8731A
OUTPUTS
38

AD+ DCBATOUT
BAT+

Project code : 91.4W101.001 SYSTEM DC/DC
TPS51120 39
CLK GEN Intel Mobile CPU
1
ICS9LPRS365
PCB P/N : 48.4W101.011 INPUTS OUTPUTS 1

4 5V_AUX_S5
Merom 4M PCB No. : 07212 DCBATOUT 3D3V_AUX_S5
5V_S5
FSB:667 or 800 MHz 3D3V_S5
5, 6, 7 Revision : -1 SYSTEM DC/DC
VRAM VRAM
16Mbx32x2 51 16Mbx32x2 52 TPS5117 42, 43
INPUTS OUTPUTS
Host BUS DCBATOUT 1D05V_S0
CRT 17
RGB CRT
GDDRIII GDDRIII 667/800MHz 1D8V_S3
700MHz 700MHz
SYSTEM DC/DC

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LVDS
DDRII TPS51100 44
LCD 18 Crestline-PM Slot 1
nVidia NB8P DDRII 667 Channel A 533/667 14 INPUTS OUTPUTS
(256MB) AGTL+ CPU I/F Power SW 1D8V_S3 0D9V_S3
PCIe x 16 27
OR DDR Memory I/F DDRII TI TPS2231 SYSTEM DC/DC

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HDMI 16 HDMI Slot 2
nVidia NB8M EXTERNAL GRAHPICS
8, 9, 10, 11, 12, 13
DDR II 667 Channel B 533/667 15 RT9018 44

2
(128MB) INPUTS OUTPUTS 2
47, 48, 49, 50 1D8V_S3 1D5V_S0
S-Video SVIDEO PCIE x 1 & USB 2.0 x 1 New Card 1D8V_S3 1D25V_S0
27
DMI I/F
100MHz VGA DC/DC
PCIE x 1 10/100 NIC 26
Marvell 88E8040
RJ45 CONN 27 TPS5117 53
1394 1394

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25
INPUTS OUTPUTS
INTEL PCIE PCIE x 1 Mini-Card x 1
Ricoh PCI 28 DCBATOUT VCC_GFX_CORE_S0
802.11a/b/g
R5C833
SD/SDIO/MMC Mini-Card x 2 29
MS/MS Pro/XD
25
CardReader
24, 25
ICH8-M PCIE x 2 & USB 2.0 x 2
WWAN&BT&Robson CPU DC/DC

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10 USB 2.0/1.1 ports
ISL6262A 40
USB 2.0 USB 2.0 x 1 Camera 18
6 PCI Express ports INPUTS OUTPUTS
High Definition Audio
DCBATOUT VCC_CORE
ATA 66/100 USB 2.0 x 1 Biometic reader30
HEADPHONE AZALIA
HP2 SATA
3
AMP 3

MAX4411 32
ACPI 1.1 PCB LAYER
USB 2.0 x 1 Bluetooth 2.1 30
VF
LPC I/F

PCI/PCI BRIDGE LPC Bus L1:TOP
19, 20, 21, 22
Lift Side: USB x 2 37
USB 2.0 x 3 L2:GND
MIC IN Azalia Right Side:USB x 1
SPI 34 L3:Signal
CODEC KBC
Digital Mic Array Sigmatel Winbond WPC8763L L4:Signal
SATA

PATA

33
STAC 922831 L5:VCC
HP1 L6:Singal
L7:GND
Thermal
Capacity Touch Int. S/W Flash ROM L8:BOT
HDD ODD & Fan
4 2CH OP AMP 23 23 Button30 Pad 36 KB36 CIR 30 2MB 30 4

SPEAKER G792 35
MAX9789A 32
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

System Block Diagram
Size Document Number Rev
A3
Hawke-Intel -1
Date: Sunday, September 09, 2007 Sheet 1 of 57
A B C D E
A B C D E

Adapter TPS51117 1D8V TPS51117 1D05V
Input Signal Output Signal Input Signal Output Signal Input Signal Output Signal
AD_IN# PM_SLP_S4# CPUCORE_ON PM_SLP_S3# CPUCORE_ON
AD_OFF (I) (O) EN_PSV(I / 5V) (O) EN_PSV(I / 5V) (O)

5V_S5 Input Power Output Power 5V_S5 Input Power Output Power
Input Power Output Power VCC VCC
1 1D8V_S3(19A) 1D05V_S0(5A) 1
AD_JK AD+ DCBATOUT (O) DCBATOUT (O)
VCC(I) VCC(O) VIN VIN
5V_AUX_S5
VCC(I)

TI TPS51100 0.9V/DDR_VREF_S3
Charger MAX8731A
Input Signal
PM_SLP_S4#
Input Signal Output Signal S5
CHARGE_OFF MAX8731_LDO
CLS (I / 3.3V) LDO (O / 5.4V) PM_SLP_S4#

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S3
ACAV_IN
(O)
BAT+SENSE AD_IA Input Power Output Power
FBSA/B (I/3.3V) (O) 5V_S5 DDR_VREF_S3
VCC(I) VCC(O)
BAT_SCL

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SCL (IO / 3.3V) 1D8V_S3 DDR_VERF_S0
VIN(I) VCC(O)
BAT_SDA ISL6262A
2
SDA (IO / 3.3V) 2
Output Power CPU_CORE
DCBATOUT
VCC (O)
RT9018A 1D5V VID Setting Output Signal
BT+ CPU_VID0
VCC (O) VID0(I / 3.3V) VGATE_PWRGD
MAX8731_ACIN VROK(O)
ACIN Input Signal Output Signal CPU_VID1
PM_SLP_S3# CPUCORE_ON VID1(I / 3.3V)

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EN(I / 5V) (O)
CPU_VID2
Input Power VID2(I / 3.3V)
AD+
DCIN (I) 5V_S5 Input Power Output Power CPU_VID3
VCC VID3(I / 3.3V)
1D5V_S0(2.2A) Output Power
1D8V_S3 (O) CPU_VID4
VIN VID4(I / 3.3V)

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CPU_VID5
VID5(I / 3.3V)
VCC_CORE_S0
TI TPS51120 3D3V/5V CPU_VID6 (Imax=47A)
RT9018A 1D25V VID6(I / 3.3V) VCC_CORE_PWR(O)
Input Signal Output Signal Input Signal
CPUCORE_ON
3
3V/5V_EN FOR Input Signal Output Signal EN (I / 3.3V) 3
51120_EN2 3.3V CPUCORE_ON PM_SLP_S3# CPUCORE_ON
PGOUT(OD / 5V) EN(I / 5V) (O)
3V/5V_EN
VF
51120_EN1 FOR Voltage Sense
5.0V 5V_S5 Input Power Output Power VCC_SENSE
VCC VSEN(I / Vcore)
1D25V_S0(2.7A)
Input Power Output Power 1D8V_S3 (O) VSS_SENSE
5V_AUX_S5 VIN RGND(I / Vcore)
DCBATOUT (O)
VIN
3D3V_AUX_S5
5V_AUX_S5 (O) Input Power
REG5V_IN(I / 5V)
5V_S5 (6A) DCBATOUT
5V (O) TPS51117 VGA_CORE VIN(I)
3.3V (O) 3D3V_S5 (5A)
5V_S0
Input Signal Output Signal VCC(I)
PM_SLP_S3# CPUCORE_ON
EN_PSV(I / 5V) (O)
3D3V_S0
VCC(I)
5V_S5 Input Power Output Power VCC_GFX_CORE_S0
VCC (18.4A)
4 4
DCBATOUT (O)
VIN
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Power Block Diagram
Size Document Number Rev
A3
Hawke-Intel -1
Date: Sunday, September 09, 2007 Sheet 2 of 57
A B C D E
A B C D E

20,22 +RTCVCC +RTCVCC

5,6,7,8,10,11,12,20,22,33,42,46 1D05V_S0 1D05V_S0

INTEL ICH8-M STRAP PIN 8,11,22,44,47,48,49 1D25V_S0 1D25V_S0

26 1D2V_LAN_S5 1D2V_LAN_S5

27 1D5V_NEW_S0 1D5V_NEW_S0

Signal Usage/When Sampled Comment XOR Chain Entrance Strap 6,11,20,21,22,27,28,29,44 1D5V_S0 1D5V_S0
HDA_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 ICH_RSVD
tp3 AZ_DOUT_ICH Description
8,11,12,14,15,43,44,45,46 1D8V_S3 1D8V_S3
1 PCIE Port Config 1 bit1, pulled low at rising edge of PWROK.When TP3 not 0 0 RSVD 1
0 1 Enter XOR Chain
Rising Edge of PWROK pulled low at rising edge of PWROK,sets bit1 of 26,27 2D5V_LAN_S5 2D5V_LAN_S5
1 0 Normal Operation(default)
RPC.PC(Config Registers:offset 224h) 1 1 Set PCIE port cofig bit1
20,30,33,35,38,39,46 3D3V_AUX_S5 3D3V_AUX_S5
HDA_SYNC PCIE Port Config 1 bit0, Sets bit0 of RPC.PC(Config Registers:Offset 224h)
Rising Edge of PWROK. 26,27 3D3V_LAN_S5 3D3V_LAN_S5
GNT2# PCIE Port Config 2 bit0, Sets bit2 of RPC.PC(Config Registers:Offset 224h) 4,8,11,14,15,16,18,19,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,40,42,45,46,47,49,50,53 3D3V_S0 3D3V_S0
Rising Edge of PWROK.
19,21,22,26,27,30,37,39,45,46 3D3V_S5 3D3V_S5
GPIO20 Reserved Weak Internal PULL-DOWN.NOTE:This signal should 18,38,39,46 5V_AUX_S5 5V_AUX_S5
not be pull HIGH.
16,17,18,22,23,30,32,34,35,36,40,44,45,46 5V_S0 5V_S0
Sampled low:Top-Block Swap mode(inverts A16 for all A16 swap override strap
GNT3# Top-Block Swap Override. cycles targeting FWH BIOS space). 22,23,29,30,34,36,37,39,42,43,44,45,53 5V_S5 5V_S5
Rising Edge of PWROK. Note: Software will not be able to clear the PCI_GNT#3 low = A16 swap override enable

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Top-Swap bit until the system is rebooted high = default 37,38,46 AD+ AD+
without GNT3# being pulled down. BOOT BIOS Strap 18,38,39,40,41,42,43,45,46,53 DCBATOUT DCBATOUT
PCI_GNT#0 SPI_CS#1 BOOT BIOS Location
GNT0# Boot BIOS Destination Controllable via Boot BIOS Destination bit 14,15,44,46 DDR_VREF_S0 DDR_VREF_S0
SPI_CS1# Selection. (Config Registers:Offset 3410h:bit 11:10). 0 1 SPI
Rising Edge of PWROK. GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC. 1 0 PCI 8,14,15,44 DDR_VREF_S3 DDR_VREF_S3
1 1 LPC(Default)
Integrated VccSus1_05

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18 +LCDVDD +LCDVDD
VccSus1_5 and VccCL1_5 Enables integrated VccSus1_05,VccSus1_5 and integrated VccSus1_05,VccSus1_5,VccCL1_5
INTVRMEN VRM Enable/Disable.Always VccCL1_5 VRM when sampled high 6,7,41 VCC_CORE_S0 VCC_CORE_S0
SM_INTVRMEN High=Enable Low=Disable
2 sampled. 2
integrated VccLan1_05VccCL1_05
LAN100_SLP
Integrated VccLAN1_05
VccCL1_05 VRM enable
Enables integrated
when sampled high
VccLAN1_05,VccCL1_05 VRM
LAN100_SLP High=Enable Low=Disable PCI ROUTING
/Disable. Always sampled.
IDSEL INT REQ GNT
SATALED# PCIE LAN REVERSAL.Rising This signal has weak internal pull-up. DEFAULE HIGH
Edge of PWROK. set bit27 of MPC.LR(Device28:Function0:Offset D8) 1394/ A
MediaCard AD25 0 0

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If sampled high, the system is strapped to the No Reboot Strap D
SPKR No Reboot. "No Reboot" mode(ICH8M will disable the TCO Timer SPKR LOW = Defaule
Rising Edge of PWROK. system reboot feature). The status is readable
via the NO REBOOT bit.(Offset:3410h:bit5)
High=No Reboot

TP3 XOR Chain Entrance.
Rising Edge of PWROK.
This signal should not be pull low unless using
XOR Chain testing. INTEL ICH8-M INTEGRATED USB TABLE
USB0 Ext Lift Side (Bottom)

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Internal Pull-Up.If sampled low,the Flash Descriptor
GPIO33/
HDA_DOCK_EN#
Flash Descriptor Security Security will be overidden.if high,the Security
Override Strap measures defined in the Flash Descriptor will be in
PULL-UPS and PULL-DOWNS USB1 Ext Lift Side (Top)
Rising Edge of PWROK. effect.
8.2K PULL HIGH USB2 Ext Right Side
This should only be used in manufacturing SIGNAL Resistor Type/Value USB3 N/A
environments HDA_BIT_CLK PULL-DOWN 20K
USB4 WWAN
HDA_RST# NONE
3
USB5 Bluetooth 3
HDA_SDIN[3:0] PULL-DOWN 20K
USB6 Camera
HDA_SDOUT PULL-DOWN 20K
VF
USB7 Biometric
HDA_SYNC PULL-DOWN 20K
USB8 Express Card
GNT[3:0] PULL-UP 20K
INTEL CRESTLINE STRAP PIN GPIO[20] PULL-DOWN 20K
USB9 3rd mini card

CFG Strap LOW 0 HIGH 1 LDA[3:0]#/FHW[3:0]# PULL-UP 20K
CFG 5
CFG 8
DMI X 2 DMI X 4
LAN_RXD[2:0]
LDRQ[0]
PULL-UP 20K
PULL-UP 20K
PCIE Routing
Low Power PCI Express Normal Low Power mode LANE1 10/100M Bit LOM
CFG 9 LDRQ[1]/GPIO23 PULL-UP 20K
PCI Express Graphics Lane Reversal Normal Mode(Lanes LANE2 MiniCard WLAN
Lane Reversal number in order) PME# PULL-UP 20K
CFG 16 LANE3 MiniCard WWAN
FSB Dynamic ODT Disabled Enabled PWRBTN# PULL-UP 20K
CFG 19 LANE4 BT/UWB/Robson
DMI Lane Reserved Normal Operation Reserved Lane SATALED# PULL-UP 20K
CFG 20 Only PCIE or SDVO PCIE and SDVO are LANE5 Express Card
Concurrent SDVO/PCIE is operation operation simultaneous SPI_CS1# PULL-UP 20K
LANE6 N/A
SDVO_CTRL_DATA NO SDVO Card SDVO Card Present SPI_CLK PULL-UP 20K
Present
SDVO Present SPI_MOSI PULL-UP 20K
4 4

CFG 12 XOR/ALL-Z SPI_MISO PULL-UP 20K
CFG 13 Wistron Corporation
LL(00) Reserved TACH_[3:0] PULL-UP 20K
LH(01) XOR Mode Enabled 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
HL(10) All Z Mode Enabled SPKR PULL-DOWN 20K Taipei Hsien 221, Taiwan, R.O.C.
HH(11) Normal Operation
TP[3] PULL-UP 20K Title

USB[9:0][P,N] PULL-DOWN 15K Table of Content
Size Document Number Rev
A3
CL_RST# TBD Hawke-Intel -1
Date: Sunday, September 09, 2007 Sheet 3 of 57
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