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5 4 3 2 1
ZE8 BLOCK DIAGRAM
PCB STACK UP
6L HDI POWER
CLOCK SYSTEM 5V/3V
D LAYER 1 : TOP D
CK505 (QFN-64) RT8206B P24
LAYER 2 : GND
PG 3
LAYER 3 : IN1 CPU Core
LAYER 4 : IN2 ISL6261A P25
FAN & THERMAL
LAYER 5 : VCC
P4 DDR Power
LAYER 6 : BOT
CPU RT8207A P26
Penryn SFF ULV DC/SC VCCP 1.05V
RT8202A P27
Micro-FCBGA956/10W P4,5
1.5V
800/1066 MHz FSB G9334/AO4466 P28
LVDS LED Panel 1.5V_S5
DDR2-SODIMM cahnge A NORTH BRIDGE Connector P23 RT9025 P28
C C
P16 VGA CRT Discharge
667/800MHZ DDR II
Cantiga SFF GS45 Connector P22 P28
DDR2-SODIMM cahnge B
TMDS HDMI Level Shifter HDMI GFX
P17 P23 Connector P23 ISL6263A P29
PG 6,7,8,9,10,11
DMI x 4
PCIE4 MINI CARD 1
2.5HDD SATA0 SOUTH BRIDGE
P21 Connector P20
PCIE PCIE5 MINI CARD 2 SIM CARD
Port 8 Connector P20 Connector P20
Touch Screen
P23
B PCIE1 Connector GLAN B
On Board USB0 Port 6 ICH9-M SFF P22 Atheros AR8131L
P21
IHDA Line Out/MIC Connector
MINI CARD 1 Port 4 P22
CODEC
P20
Speaker Speaker Connector
Realtek ALC269X
MINI CARD 2 Port 2 USB P19
P20
Digital MIC LED Panel
PG 12,13,14,15
CCD Port 7 P18 Connector P23
P23
LPC
Bule Tooth Port 5
EC
P22 8x16 Keyboard
Winbond WPCE775LA0DG
Connector P22
A Port 0 P19 A
Connector
On Board USB2
Port 1 SPI PS/2
On Board USB3
FLASH TouchPAD Quanta Computer Inc.
Card Reader Port 3
2Mbytes Connector PROJECT : ZE8
Alcor AU6433 P22 Size Document Number Rev
P19 P22 1A
Schematic Block Diagram
Date: Tuesday, September 29, 2009 Sheet 1 of 32
5 4 3 2 1
5 4 3 2 1
ZE8 Power On Sequence BOM naming rule
From AC,Battery VIN
Items Function Name Description
D
+5VPCU +3VPCU D
1 With HDMI HD@
From PWM SYS_HWPG(PCU)
2 Without HDMI NHD@
From Power Button NBSWON#
3 3G Module 3G@
From EC S5_ON
4
+3V_S5,1.5V_S5
5
+5V_S5
6
From EC to SB RSMRST#
From SB to EC SUSB#,SUSC#
SUSON
From EC SUSON
+3VSUS +1.8VSUS +SMDDR_VREF +SMDDR_VTERM
>5ms ICH9M SFF SMBUS Table
From PWM HWPG_1.8V (SUS)
C C
From EC MAINON >5ms
MAINON CLK GEN RAM Mini Card (WLAN/WMAX) Mini Card (3G) G sensor
+5V +3V +1.5V +1.05V (SMB_DATA) / (SMB_CLK) (+3V_S5) V V V V V
From PWM HWPG_1.5V HWPG_1.05V Power Plane +3V +3V +3V +3VSUS +3V
>10ms
From PWM HWPG(MPWROK) VRON MOS CKT Stuff Stuff Stuff Stuff Stuff
From EC PWROK_EC
>5ms
From EC VRON
+VCC_CORE
From PWM to U5 VR_PWRGD_CK410#
From U5 to SB VR_PWRGD_CLKEN EC SMBUS Table
From SB to CLK GEN VR_PWRGD_CK410
Battery CPU thermal Sensor EC EEPROM
B From PWM to U7 DELAY_VR_PWRGOOD(CPU PWRGD) B
EC775 SDATA1/SCLK1(+3VPCU) V
From U7 to SB ICH_PWRGD EC775 SDATA2/SCLK2(+3V) V
From SB to CPU H_PWRGOOD EC775 SDATA3/SCLK3(+3VPCU) V
Power Plane +3VPCU +3V +3VPCU
From SB to NB PLTRST#,PCIRST#
MOS CKT X X X
From NB to CPU CPURST#
A A
Quanta Computer Inc.
PROJECT : ZE8
Size Document Number Rev
1A
Power Sequence/ BOM Rule
Date: Tuesday, September 29, 2009 Sheet 2 of 32
5 4 3 2 1
5 4 3 2 1
+3V +3V
Clock Generator (CLK)
R152 R157
+1.05V +1.05V_VDD_CLK
2
2
Q5 Q6
4.7K_4 4.7K_4
L16 PBY160808T-301Y-N/2A/300ohm_6 (16,19,21) SMBDT1 1 3PDAT_SMB PDAT_SMB (14,19) (16,19,21) SMBCK1 1 3PCLK_SMB PCLK_SMB (14,19)
2N7002 2N7002
C237 C230 C234 C238 C239 C236
D D
R153 *0_4 R158 *0_4
+3V_VDD_CLK
10u/10V_8 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 U7
9 VDD_PCI NC 55
16 VDD_48 SMBCK1 +3V
23 VDD_PLL3 CK505 SCLK 7
SMBDT1
4 VDD_REF SDA 6
QFN PM_STPPCI# R149 2.2K_4
+3V +3V_VDD_CLK 46 45 PM_STPPCI# PM_STPCPU# R148 2.2K_4
+1.05V_VDD_CLK VDD_SRC SRC5/PCI_STOP# PM_STPPCI# (14)
62 44 PM_STPCPU# PM_STPCPU# (14)
L17 PBY160808T-301Y-N/2A/300ohm_6 VDD_CPU SRC5#/CPU_STOP#
19 61 CLK_CPU_BCLK CLK_CPU_BCLK (4)
C240 C223 C227 C228 C232 C231 VDD_96_IO CPU0 CLK_CPU_BCLK#
27 VDD_PLL3_IO CPU0# 60 CLK_CPU_BCLK# (4)
33 VDD_SRC_IO_1
52 58 CLK_MCH_BCLK CLK_MCH_BCLK (6)
10u/10V_8 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 *0.1u/10V_4 0.1u/10V_4 VDD_SRC_IO_3 CPU1 CLK_MCH_BCLK#
43 VDD_SRC_IO_2 CPU1# 57 CLK_MCH_BCLK# (6)
56 VDD_CPU_IO
SRC8/ITP 54
SRC8#/ITP# 53
(14) CLKREQ#_SATA CLKREQ#_SATA R121 475/F_4 CR#_A 8 41 PECLK_MINI2 PECLK_MINI2 (19)
PCI0/CR#_A SRC10 PECLK_MINI2#
SRC10# 42 PECLK_MINI2# (19)
(21) CLKREQ#_LAN CLKREQ#_LAN R138 475/F_4 CR#_B 10
C PCI1/CR#_B CR#_H R147 3G@475/F_4 C
SRC11/CR#_H 40 CLKREQ#_MINI2 (19)
(19) PCLK_DEBUG PCLK_DEBUG 11 39 CR#_G R146 475/F_4 CLKREQ#_MINI1 CLKREQ#_MINI1 (19)
PCI2/TME SRC11#/CR#_G
12 37 PECLK_MINI1 PECLK_MINI1 (19)
PCI3 SRC9 PECLK_MINI1#
SRC9# 38 PECLK_MINI1# (19)
(18) PCICLK_EC PCICLK_EC R117 33_4 PCICLK_EC_R 13 PCI4/LCDCLK_SEL
SRC7/CR#_F 51
(13) PCLK_ICH PCLK_ICH R118 33_4 PCLK_ICH_R 14 50 CR#_E R143 475/F_4 CLKREQ#_MCH CLKREQ#_MCH (7)
0603 : card reader PCIF5/ITP_EN SRC7#/CR#_E +3V
use external crystal CG_XIN 3 48 PECLK_3GPLL PECLK_3GPLL (7)
CLK48_CARD R133 *22_4 XTAL_IN SRC6 PECLK_3GPLL# CR#_A R131 10K_4
(21) CLK48_CARD SRC6# 47 PECLK_3GPLL# (7)
CG_XOUT 2 CR#_B R132 10K_4
XTAL_OUT PECLK_LAN CR#_E R142 10K_4
SRC4 34 PECLK_LAN (21)
(14) CLK48_ICH CLK48_ICH R124 22_4 CLK48_ICH_R 17 35 PECLK_LAN# PECLK_LAN# (21) CR#_G R145 10K_4
USB_48/FSA SRC4# CR#_H R144 3G@10K_4
FSB 64 31 PECLK_ICH PECLK_ICH (13)
FSB/TEST/MODE SRC3/CR#_C PECLK_ICH#
SRC3#/CR#_D 32 PECLK_ICH# (13)
(14) CLK14_ICH CLK14_ICH R126 33_4 CLK14_ICH_R 5 Clock Request Table
REF0/FSC/TESTSEL PECLK_SATA
65 VSS_BODY SRC2/SATA 28 PECLK_SATA (12) CLKREQ# MAPPING Control
15 29 PECLK_SATA# PECLK_SATA# (12) 0 1
VSS_PCI SRC2#/SATA# CR#_A SRC0 SRC2 SATA
18 VSS_48
22 24 DREFSSCLK DREFSSCLK (7) CR#_B LCDCLK SRC4 LAN
Layout notice: placed within 500-mils of CK505M VSS_IO SRC1/SE1 DREFSSCLK# CR#_C SRC0 SRC2 N/A
26 VSS_PLL3 SRC1#/SE2 25 DREFSSCLK# (7)
B 59 CR#_D LCDCLK SRC4 N/A B
C226 27p/50V_4 CG_XIN VSS_CPU DREFCLK CR#_E SRC6 MCH
30 VSS_SRC1 SRC0/DOT96 20 DREFCLK (7)
36 21 DREFCLK# DREFCLK# (7) CR#_F SRC8 N/A
VSS_SRC2 SRC0#/DOT96#
2
Y1 49 CR#_G SRC9 MINI1
VSS_SRC3 VR_PWRGD_CK410 CR#_H SRC10 MINI2
1 VSS_REF CKPWRGD/PWRDWN# 63 VR_PWRGD_CK410 (14)
14.318MHZ SLG8SP513
1
C225 33p/50V_4 CG_XOUT
SLG8SP513VTR ,ICS9LPRS365BKLFT SLG8SP513VTR ICS9LPRS365
(AL8SP513000) (ALPRS365000) PULL HIGH PULL DOWN
+3V SMbus address D2 Pin 11 PCI2/TME PCI2/TME NO OVERCLOCKING (default) NORMAL RUN
If XDP is not implemented the 1-k