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5 4 3 2 1
ZO3 SYSTEM BLOCK DIAGRAM
D
TV-OUT VCORE(ISL6262A) +2.5V/ +1.25VM/ +1.25V/ +1.5V D
P14 SMDDR_VREF/ SMDDR_VTERM
P25
TFT LCD Panel
CPU CPU Fan
WXGA AMD S1g1 Thermal Sensor 5V/3.3V (TPS51120) VGA-Core (MAX 1993)
P4 P22 +1.2V
P14
uFCPGA638 P24 P26
Turion 64 Dual-Core/
Sempron Single-Core DDRII
CRT Dual Channel DDR2 DISCHARGE BATTERY SELECT
P14
SO-DIMM 0
P2,3,4,5 533/667 MHz
SO-DIMM 1 P28 P23
P6
HT LINK
USB 2.0 +1.8V BATTERYCHARGER
LVDS
INT or EV (ISL6251)
TV-out PCI-Express 16X P27 P23
selector Resistor MXM
P14 CRT
Bluetooth
P13 P16
TV-out n-Vidia USB
C C
LVDS MCP67 USB Port x 4
P16
VGA Mini Card / New Card
CCD WLAN
P14
P17 P17
SATA0
HDD (SATA) PCI-Express
P18 LCI
PCI Bus PCIE-6
PATA X'TAL
25M
Azalia P7,8,9,10,11,12
ODD (PATA) X'TAL24.576MHZ
P18
X'TAL
32.768KHZ
LAN PHY
Realtek RTL8211B
1394 +Cardreader
Int MIC LPC Controller P15
B B
Ricoh R5C833
Azalia AudioController Transformer
X'TAL P20
RealTek ALC268 32.768K P15
Audio Amplifier
P19 P19 EC (WPC8769LDG)
P21
RJ45/11
IEEE 1394 Port Media Card Reader P15
P20 P20
MIC Jack Line in
P19 P19
SPI ROM
P21
Connector
Speaker Phone Jack MDC 1.5 Touch Pad
P19 P19 P19
P18
A A
Keyboard
P22
PROJECT : ZO3
Quanta Computer Inc.
Size Document Number Rev
Block Diagram 1A
Date: Wednesday, April 25, 2007 Sheet 1 of 30
5 4 3 2 1
5 4 3 2 1
HT_RXD#[15..0] HT_TXD[15..0]
(7) HT_RXD#[15..0] (7) HT_TXD[15..0]
HT_RXD[15..0] HT_TXD#[15..0]
(7) HT_RXD[15..0] (7) HT_TXD#[15..0]
D D
PROCESSOR HYPERTRANSPORT INTERFACE
VLDT_Ax AND VLDT_Bx ARE CONNECTED TO THE LDT_RUN POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE
VLDT_RUN
U21A
C516
D4 VLDT_A3 VLDT_B3 AE5
D3 VLDT_A2 VLDT_B2 AE4
D2 VLDT_A1 VLDT_B1 AE3
D1 AE2 4.7U_6
VLDT_A0 VLDT_B0
HT_RXD15 N5 T4 HT_TXD15
HT_RXD#15P5 L0_CADIN_H15 L0_CADOUT_H15 HT_TXD#15
L0_CADIN_L15 L0_CADOUT_L15 T3
HT_RXD14 M3 V5 HT_TXD14
HT_RXD#14 L0_CADIN_H14 L0_CADOUT_H14 HT_TXD#14
C M4 L0_CADIN_L14 L0_CADOUT_L14 U5 C
HT_RXD13 L5 V4 HT_TXD13
HT_RXD#13 L0_CADIN_H13 L0_CADOUT_H13 HT_TXD#13
M5 L0_CADIN_L13 L0_CADOUT_L13 V3
HT_RXD12 K3 Y5 HT_TXD12 +1.2V_HT VLDT_RUN
HT_RXD#12K4 L0_CADIN_H12 L0_CADOUT_H12 HT_TXD#12
L0_CADIN_L12 L0_CADOUT_L12 W5
HT_RXD11 H3 AB5 HT_TXD11 L41
HT_RXD#11H4 L0_CADIN_H11 L0_CADOUT_H11 HT_TXD#11
L0_CADIN_L11 L0_CADOUT_L11 AA5
HT_RXD10 G5 AB4 HT_TXD10 FBJ3216HS800_1206
HT_RXD#10H5 L0_CADIN_H10 L0_CADOUT_H10 HT_TXD#10
L0_CADIN_L10 L0_CADOUT_L10 AB3
HT_RXD9 F3 AD5 HT_TXD9 L40
HT_RXD#9 F4 L0_CADIN_H9 L0_CADOUT_H9 HT_TXD#9
L0_CADIN_L9 L0_CADOUT_L9 AC5
HT_RXD8 E5 AD4 HT_TXD8 FBJ3216HS800_1206
HT_RXD#8 F5 L0_CADIN_H8 L0_CADOUT_H8 HT_TXD#8
L0_CADIN_L8 L0_CADOUT_L8 AD3
HT_RXD7 N3 T1 HT_TXD7 80 ohm(4A) C488 C493 C492 C491 C489 C490
HT_RXD#7 N2 L0_CADIN_H7 L0_CADOUT_H7 HT_TXD#7 4.7U_6 4.7U_6 .22U_4 .22U_4 180P_4 180P_4
L0_CADIN_L7 L0_CADOUT_L7 R1
HT_RXD6 L1 U2 HT_TXD6
HT_RXD#6 M1 L0_CADIN_H6 L0_CADOUT_H6 HT_TXD#6
L0_CADIN_L6 L0_CADOUT_L6 U3
HT_RXD5 L3 V1 HT_TXD5
HT_RXD#5 L2 L0_CADIN_H5 L0_CADOUT_H5 HT_TXD#5
L0_CADIN_L5 L0_CADOUT_L5 U1
HT_RXD4 J1 HT_TXD4
HT_RXD#4 K1 L0_CADIN_H4 L0_CADOUT_H4 W2
W3 HT_TXD#4 LAYOUT: Place bypass cap on topside of board
HT_RXD3 G1 L0_CADIN_L4 L0_CADOUT_L4 HT_TXD3
L0_CADIN_H3 L0_CADOUT_H3 AA2 NEAR HT POWER PINS THAT ARE NOT CONNECTED DIRECTLY
HT_RXD#3 H1 AA3 HT_TXD#3 TO DOWNSTREAM HT DEVICE, BUT CONNECTED INTERNALLY
HT_RXD2 G3 L0_CADIN_L3 L0_CADOUT_L3 HT_TXD2
L0_CADIN_H2 L0_CADOUT_H2 AB1 TO OTHER HT POWER PINS
B HT_RXD#2 G2 AA1 HT_TXD#2 PLACE CLOSE TO VLDT0 POWER PINS B
HT_RXD1 E1 L0_CADIN_L2 L0_CADOUT_L2 HT_TXD1
L0_CADIN_H1 L0_CADOUT_H1 AC2
HT_RXD#1 F1 AC3 HT_TXD#1
HT_RXD0 E3 L0_CADIN_L1 L0_CADOUT_L1 HT_TXD0
L0_CADIN_H0 L0_CADOUT_H0 AD1
HT_RXD#0 E2 AC1 HT_TXD#0
L0_CADIN_L0 L0_CADOUT_L0
(7) HT_CPU_UPCLK1 J5 L0_CLKIN_H1 L0_CLKOUT_H1 Y4 HT_CPU_DWNCLK1 (7)
(7) HT_CPU_UPCLK#1 K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 HT_CPU_DWNCLK#1 (7)
J3 Y1
VLDT_RUN (7) HT_CPU_UPCLK0 J2
L0_CLKIN_H0 L0_CLKOUT_H0
W1
HT_CPU_DWNCLK0 (7)
(7) HT_CPU_UPCLK#0 L0_CLKIN_L0 L0_CLKOUT_L0 HT_CPU_DWNCLK#0 (7)
R369 51_4 HT_CTLIN1_P P3 T5 HT_CPU_DWNCTL1
HT_CTLIN1_N L0_CTLIN_H1 L0_CTLOUT_H1 T31
P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 HT_CPU_DWNCTL#1
R370 51_4 T30
(7) HT_CPU_UPCTL0 N1 L0_CTLIN_H0 L0_CTLOUT_H0 R2 HT_CPU_DWNCTL0 (7)
(7) HT_CPU_UPCTL#0 P1 L0_CTLIN_L0 L0_CTLOUT_L0 R3 HT_CPU_DWNCTL#0 (7)
Athlon 64 S1
Processor Socket
A A
PROJECT : ZO3
Quanta Computer Inc.
Size Document Number Rev
ATHLON64 HT I/F 1A
Date: Wednesday, April 25, 2007 Sheet 2 of 30
5 4 3 2 1
A B C D E
+1.8VSUS
VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE
Processor DDR2 Memory Interface
R229
2K/F_4
U21C
M_B_DQ63 AD11 AA12 M_A_DQ63
(6) M_B_DQ[0..63] MB_DATA63 MA_DATA63 M_A_DQ[0..63] (6)
M_B_DQ62 AF11 AB12 M_A_DQ62
CPU_M_VREF M_B_DQ61 MB_DATA62 MA_DATA62 M_A_DQ61
AF14 MB_DATA61 MA_DATA61 AA14
M_B_DQ60 AE14 AB14 M_A_DQ60
4
M_B_DQ59 MB_DATA60 MA_DATA60 M_A_DQ59 4
Y11 MB_DATA59 MA_DATA59 W11
C241 C300 R230 M_B_DQ58 AB11 Y12 M_A_DQ58
M_B_DQ57 MB_DATA58 MA_DATA58 M_A_DQ57
AC12 MB_DATA57 MA_DATA57 AD13
.1U_4 1000P_4 2K/F_4 M_B_DQ56 AF13 AB13 M_A_DQ56
M_B_DQ55 MB_DATA56 MA_DATA56 M_A_DQ55
AF15 MB_DATA55 MA_DATA55 AD15
M_B_DQ54 AF16 AB15 M_A_DQ54
M_B_DQ53 MB_DATA54 MA_DATA54 M_A_DQ53
AC18 MB_DATA53 MA_DATA53 AB17
+1.8VSUS M_B_DQ52 AF19 Y17 M_A_DQ52
+SMDDR_VTERM M_B_DQ51 MB_DATA52 MA_DATA52 M_A_DQ51
AD14 MB_DATA51 MA_DATA51 Y14
U21B M_B_DQ50 AC14 W14 M_A_DQ50
MB_DATA50 MA_DATA50
2
M_B_DQ49 AE18 W16 M_A_DQ49
R412 M_B_DQ48 MB_DATA49 MA_DATA49 M_A_DQ48
AD18 MB_DATA48 MA_DATA48 AD17
39.2/F_4 W17 D10 M_B_DQ47 AD20 Y18 M_A_DQ47
MEMVREF VTT1 M_B_DQ46 MB_DATA47 MA_DATA47 M_A_DQ46
VTT2 C10 AC20 MB_DATA46 MA_DATA46 AD19
VTT_SENSE Y10 B10 M_B_DQ45 AF23 AD21 M_A_DQ45
T35
1
VTT_SENSE VTT3 M_B_DQ44 MB_DATA45 MA_DATA45 M_A_DQ44
VTT4 AD10 AF24 MB_DATA44 MA_DATA44 AB21
W10 M_B_DQ43 AF20 AB18 M_A_DQ43
M_ZN VTT5 M_B_DQ42 MB_DATA43 MA_DATA43 M_A_DQ42
AE10 MEMZN VTT6 AC10 AE20 MB_DATA42 MA_DATA42 AA18
M_ZP AF10 AB10 M_B_DQ41 AD22 AA20 M_A_DQ41
MEMZP VTT7 M_B_DQ40 MB_DATA41 MA_DATA41 M_A_DQ40
VTT8 AA10 AC22 MB_DATA40 MA_DATA40 Y20
A10 M_B_DQ39 AE25 AA22 M_A_DQ39
VTT9 MB_DATA39 MA_DATA39
2
M_B_DQ38 AD26 Y22 M_A_DQ38
R413 M_B_DQ37 MB_DATA38 MA_DATA38 M_A_DQ37
(6) M_A_CS#3 V19 MA0_CS_L3 MA0_CLK_H2 Y16 M_CLKOUT1 (6) AA25 MB_DATA37 MA_DATA37 W21
39.2/F_4 J22 AA16 M_B_DQ36 AA26 W22 M_A_DQ36
(6) M_A_CS#2 MA0_CS_L2 MA0_CLK_L2 M_CLKOUT1# (6) MB_DATA36 MA_DATA36
V22 E16 M_B_DQ35 AE24 AA21 M_A_DQ35
(6) M_A_CS#1 MA0_CS_L1 MA0_CLK_H1 M_CLKOUT0 (6) MB_DATA35 MA_DATA35
T19 F16 M_B_DQ34 AD24 AB22 M_A_DQ34
(6) M_A_CS#0 M_CLKOUT0# (6)
1
MA0_CS_L0 MA0_CLK_L1 M_B_DQ33 MB_DATA34 MA_DATA34 M_A_DQ33
AA23 MB_DATA33 MA_DATA33 AB24
Y26 AF18 M_B_DQ32 AA24 Y24 M_A_DQ32
(6) M_B_CS#3 MB0_CS_L3 MB0_CLK_H2 M_CLKOUT4 (6) MB_DATA32 MA_DATA32
J24 AF17 M_B_DQ31 G24 H22 M_A_DQ31
(6) M_B_CS#2 MB0_CS_L2 MB0_CLK_L2 M_CLKOUT4# (6) MB_DATA31 MA_DATA31
W24 A17 M_B_DQ30 G23 H20 M_A_DQ30
(6) M_B_CS#1 MB0_CS_L1 MB0_CLK_H1 M_CLKOUT3 (6) MB_DATA30 MA_DATA30
U23 A18 M_B_DQ29 D26 E22 M_A_DQ29
(6) M_B_CS#0 MB0_CS_L0 MB0_CLK_L1 M_CLKOUT3# (6) MB_DATA29 MA_DATA29
M_B_DQ28 C26 E21 M_A_DQ28
M_B_DQ27 MB_DATA28 MA_DATA28 M_A_DQ27
(6) M_CKE3 H26 MB_CKE1 MB0_ODT1 W23 M_ODT3 (6) G26 MB_DATA27 MA_DATA27 J19
J23 W26 M_B_DQ26 G25 H24 M_A_DQ26
(6) M_CKE2 MB_CKE0 MB0_ODT0 M_ODT2 (6) MB_DATA26 MA_DATA26
M_B_DQ25 M_A_DQ25
To SODIMM socket A (near)
J20 V20 E24 F22
To SODIMM socket B (Far)
(6) M_CKE1 MA_CKE1 MA0_ODT1 M_ODT1 (6) MB_DATA25 MA_DATA25
J21 U19 M_B_DQ24 E23 F20 M_A_DQ24
(6) M_CKE0 MA_CKE0 MA0_ODT0 M_ODT0 (6) MB_DATA24 MA_DATA24
M_B_DQ23 C24 C23 M_A_DQ23
(6) M_A_A[0..15] MB_DATA23 MA_DATA23
3 M_A_A15 K19 J25 M_B_A15 M_B_DQ22 B24 B22 M_A_DQ22 3
MA_ADD15 MB_ADD15 M_B_A[0..15] (6) MB_DATA22 MA_DATA22
M_A_A14 K20 J26 M_B_A14 M_B_DQ21 C20 F18 M_A_DQ21
M_A_A13 MA_ADD14 MB_ADD14 M_B_A13 M_B_DQ20 MB_DATA21 MA_DATA21 M_A_DQ20
V24 MA_ADD13 MB_ADD13 W25 B20 MB_DATA20 MA_DATA20 E18
M_A_A12 K24 L23 M_B_A12 M_B_DQ19 C25 E20 M_A_DQ19
M_A_A11 MA_ADD12 MB_ADD12 M_B_A11 M_B_DQ18 MB_DATA19 MA_DATA19 M_A_DQ18
L20 MA_ADD11 MB_ADD11 L25 D24 MB_DATA18 MA_DATA18 D22
M_A_A10 R19 U25 M_B_A10 M_B_DQ17 A21 C19 M_A_DQ17
M_A_A9 MA_ADD10 MB_ADD10 M_B_A9 M_B_DQ16 MB_DATA17 MA_DATA17 M_A_DQ16
L19 MA_ADD9 MB_ADD9 L24 D20 MB_DATA16 MA_DATA16 G18
M_A_A8 L22 M26 M_B_A8 M_B_DQ15 D18 G17 M_A_DQ15
M_A_A7 MA_ADD8 MB_ADD8 M_B_A7 M_B_DQ14 MB_DATA15 MA_DATA15 M_A_DQ14
L21 MA_ADD7 MB_ADD7 L26 C18 MB_DATA14 MA_DATA14 C17
M_A_A6 M19 N23 M_B_A6 M_B_DQ13 D14 F14 M_A_DQ13
M_A_A5 MA_ADD6 MB_ADD6 M_B_A5 M_B_DQ12 MB_DATA13 MA_DATA13 M_A_DQ12
M20 MA_ADD5 MB_ADD5 N24 C14 MB_DATA12 MA_DATA12 E14
M_A_A4 M24 N25 M_B_A4 M_B_DQ11 A20 H17 M_A_DQ11
M_A_A3 MA_ADD4 MB_ADD4 M_B_A3 M_B_DQ10 MB_DATA11 MA_DATA11 M_A_DQ10
M22 MA_ADD3 MB_ADD3 N26 A19 MB_DATA10 MA_DATA10 E17
M_A_A2 N22 P24 M_B_A2 M_B_DQ9 A16 E15 M_A_DQ9
M_A_A1 MA_ADD2 MB_ADD2 M_B_A1 M_B_DQ8 MB_DATA9 MA_DATA9 M_A_DQ8
N21 MA_ADD1 MB_ADD1 P26 A15 MB_DATA8 MA_DATA8 H15
M_A_A0 R21 T24 M_B_A0 M_B_DQ7 A13 E13 M_A_DQ7
MA_ADD0 MB_ADD0 M_B_DQ6 MB_DATA7 MA_DATA7 M_A_DQ6
D12 MB_DATA6 MA_DATA6 C13
K22 K26 M_B_BS#2 (6) M_B_DQ5 E11 H12 M_A_DQ5
(6) M_A_BS#2 MA_BANK2 MB_BANK2 MB_DATA5 MA_DATA5
R20 T26 M_B_BS#1 (6) M_B_DQ4 G11 H11 M_A_DQ4
(6) M_A_BS#1 MA_BANK1 MB_BANK1 MB_DATA4 MA_DATA4
T22 U26 M_B_BS#0 (6) M_B_DQ3 B14 G14 M_A_DQ3
(6) M_A_BS#0 MA_BANK0 MB_BANK0 MB_DATA3 MA_DATA3
M_B_DQ2 A14 H14 M_A_DQ2
M_B_DQ1 MB_DATA2 MA_DATA2 M_A_DQ1
(6) M_A_RAS# T20 MA_RAS_L MB_RAS_L U24 M_B_RAS# (6) A11 MB_DATA1 MA_DATA1 F12
U20 V26 M_B_DQ0 C11 G12 M_A_DQ0
(6) M_A_CAS# MA_CAS_L MB_CAS_L M_B_CAS# (6) MB_DATA0 MA_DATA0
(6) M_A_WE# U21 MA_WE_L MB_WE_L U22 M_B_WE# (6)
M_B_DM7 AD12 Y13 M_A_DM7
M_B_DM6 MB_DM7 MA_DM7 M_A_DM6