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Note Before using this information and the product it supports, be sure to read the general information under Appendix C.

First Edition (April 1998)
The following paragraph does not apply to the United Kingdom or any country where such provisions are inconsistent with local law: INTERNATIONAL BUSINESS MACHINES CORPORATION PROVIDES THIS PUBLICATION "AS IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE LIMITED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Some states do not allow disclaimer or express or implied warranties in certain transactions; therefore, this statement may not apply to you. This publication could include technical inaccuracies or typographical errors. Changes are periodically made to the information herein; these changes will be incorporated in new editions of the publication. IBM may make improvements or changes to the products or the programs described in this publication at any time. It is possible that this publication may contain references to, or information about, IBM products (machines and programs), programming, or services that are not announced in your country. Such references or information must not be construed to mean that IBM intends to announce such IBM products, programming, or services in your country. Requests for technical information about IBM products should be made to your IBM authorized dealer or your IBM marketing representative. Copyright International Business Machines Corporation 1998. All rights reserved. Note to US Government Users ­ Documentation related to restricted rights ­ Use, duplication, or disclosure is subject to restrictions set forth in GSA ADP Schedule Contract with IBM Corp.

Contents
Figures Preface
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vii ix

Section 1. System Overview . . . . . . . . . . . . . . . . . Description System Board Devices and Features System Board I/O Address Map . . Specifications . . . . . . . . . . . . . Performance Specifications . . . Physical Specifications . . . . . . Electrical Specifications . . . . . Acoustical Readings . . . . . . . Power Supply . . . . . . . . . . . . . Voltages . . . . . . . . . . . . . . Output Protection . . . . . . . . . Voltage Sequencing . . . . . . . . Power Supply Connector . . . . . Battery Pack . . . . . . . . . . . . .

1-1 1-2 1-3 1-5 1-7 1-7 1-8 1-9 1-9 1-10 1-10 1-11 1-11 1-11 1-12 2-1 2-2 2-2 2-2 2-3 2-3 2-4 2-4 2-4 2-4 2-6 2-7 2-8 2-8 2-11 2-14 2-15 2-15 2-15 2-16 2-17

Section 2. System Board . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . Microprocessor . . . . . . . . . . . . . . . . . . . . . Cache Memory Operation . . . . . . . . . . . . . Cacheable Address Space . . . . . . . . . . . . . Bus Adapter . . . . . . . . . . . . . . . . . . . . . . . Keyboard/Mouse Connector . . . . . . . . . . . . . . Signals . . . . . . . . . . . . . . . . . . . . . . . . Connector . . . . . . . . . . . . . . . . . . . . . . Scan Codes . . . . . . . . . . . . . . . . . . . . . Keyboard ID . . . . . . . . . . . . . . . . . . . . . Displayable Characters and Symbols . . . . . . . Hard Disk Drive Connector . . . . . . . . . . . . . . External Bus Connector . . . . . . . . . . . . . . . . UltraSlim Bay Connector . . . . . . . . . . . . . . . Diskette Drive and Controller . . . . . . . . . . . . . Memory . . . . . . . . . . . . . . . . . . . . . . . . . ROM Subsystem . . . . . . . . . . . . . . . . . . RAM Subsystem . . . . . . . . . . . . . . . . . . . System Memory Map . . . . . . . . . . . . . . . . System Board Memory for the DIMM Connectors

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Copyright IBM Corp. 1998

iii

RT/CMOS RAM . . . . . . . . . . . . . . Miscellaneous System Functions and Ports Nonmaskable Interrupt (NMI) . . . . . . System Control Port A (Hex 0092) . . . System Control Port B (Hex 0061) . . . Power-On Password . . . . . . . . . . . Other Passwords . . . . . . . . . . . . . Selectable Drive-Startup Sequence . . . Hardware Compatibility . . . . . . . . . . . Error Codes . . . . . . . . . . . . . . . . . . Section 3. Subsystems . . . . . Video Subsystem . . . . . . . . . . Video Modes . . . . . . . . . . . Modem Subsystem . . . . . . . . . ThinkPad Modem . . . . . . . . MIDI Port Function . . . . . . . Sound Blaster Support Function Telephony (Modem) Function . Audio Subsystem . . . . . . . . . . MIDI Port Function . . . . . . . Sound Blaster Support Function Audio Port Specifications . . . . Infrared (IR) Subsystem . . . . . . IRQ Level and DMA Channel . PC Card Subsystem . . . . . . . . Pin Assignments . . . . . . . . . IDE Channel on the UltraSlim Bay MIDI/Joystick Port . . . . . . . . . MIDI Interface . . . . . . . . . . Joystick Interface . . . . . . . . Appendix A. System Resources
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2-18 2-28 2-28 2-29 2-30 2-31 2-31 2-32 2-33 2-34 3-1 3-2 3-3 3-5 3-5 3-5 3-5 3-6 3-6 3-6 3-7 3-7 3-8 3-8 3-9 3-10 3-12 3-12 3-12 3-13 A-1

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Appendix B. System Management API (SMAPI) BIOS Overview . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . Header Image . . . . . . . . . . . . . . . . . . . . . . . . . Calling Convention . . . . . . . . . . . . . . . . . . . . . . Parameter Structure . . . . . . . . . . . . . . . . . . . Calling Convention Pseudo Code . . . . . . . . . . . . Return Codes . . . . . . . . . . . . . . . . . . . . . . . . . Function Description . . . . . . . . . . . . . . . . . . . . . System Information Service . . . . . . . . . . . . . . . System Configuration Service . . . . . . . . . . . . . . iv

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B-1 B-3 B-4 B-6 B-6 B-10 B-11 B-12 B-12 B-22

Power Management Service Event Bit Definition . . . . . Samples . . . . . . . . . . . Function Declaration . . . . Installation Check . . . . . . BIOS Call . . . . . . . . . . . Appendix C. Appendix C Index

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B-29 B-34 B-53 B-57 B-58 B-62 C-1 X-1

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v

vi

Figures
1-1. 1-2. 1-3. 1-4. 1-5. 1-6. 1-7. 1-8. 1-9. 1-10. 2-1. 2-2. 2-3. 2-4. 2-5. 2-6. 2-7. 2-8. 2-9. 2-10. 2-11. 2-12. 2-13. 2-14. 2-15. 2-16. 2-17. 2-18. 2-19. 2-20. 2-21. 2-22. 2-23. 2-24. 2-25. 2-26. 2-27. 2-28. 2-29. Model and Submodel Bytes . . . . . . . . . . . . . System Board Devices and Features . . . . . . . . System Board I/O Address Map . . . . . . . . . . . Performance Specifications . . . . . . . . . . . . . . Physical Specifications . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . Acoustical Readings . . . . . . . . . . . . . . . . . . Power Supply Maximum Current . . . . . . . . . . Voltage Pin Assignments for the 56W AC Adapter Lithium-Ion Battery Pack Specifications . . . . . . . Keyboard and Mouse Signals . . . . . . . . . . . . Keyboard/Mouse Connector Pin Assignments . . . Key Numbers for the 85-Key Keyboard . . . . . . . Key Numbers for the 86-Key Keyboard . . . . . . . Key Numbers for the 90-Key Keyboard . . . . . . . Key Numbers for the External Numeric Keypad . . Hard Disk Drive Connector Pin Assignments . . . 240-Pin External Bus Connector Pin Assignments UltraSlim Bay Connector Pin Assignments . . . . . Diskette Drive Read, Write, and Format Capabilities System Memory Map . . . . . . . . . . . . . . . . . DIMM Adapter Card Memory Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . RT/CMOS RAM Address Map . . . . . . . . . . . . RT/CMOS Address and NMI Mask Register (Hex 0070) . . . . . . . . . . . . . . . . . . . . . . . . . . RT/CMOS Data Register (Hex 0071) . . . . . . . . Real-Time Clock Bytes (Hex 000­00D) . . . . . . . Status Register A (Hex 00A) . . . . . . . . . . . . . Status Register B (Hex 00B) . . . . . . . . . . . . . Status Register C (Hex 00C) . . . . . . . . . . . . . Status Register D (Hex 00D) . . . . . . . . . . . . . Diagnostic Status Byte (Hex 00E) . . . . . . . . . . Diskette Drive Type Byte (Hex 010) . . . . . . . . . Diskette Drive Type Bits 7­4 . . . . . . . . . . . . . Hard Disk Type Byte (Hex 011) . . . . . . . . . . . Hard Disk Drive Type 2 (Bits 7­4) . . . . . . . . . . Hard Disk Drive Type 3 (Bits 3­0) . . . . . . . . . . Hard Disk Drive Type Byte . . . . . . . . . . . . . . Equipment Byte . . . . . . . . . . . . . . . . . . . . Installed Diskette Drive Bits . . . . . . . . . . . . .
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1-2 1-3 1-5 1-7 1-8 1-9 1-9 1-10 1-11 1-12 2-4 2-4 2-5 2-5 2-6 2-7 2-8 2-9 2-12 2-14 2-16 2-17 2-18 2-19 2-19 2-21 2-21 2-22 2-23 2-23 2-24 2-25 2-25 2-25 2-25 2-25 2-26 2-26 2-26

Copyright IBM Corp. 1998

vii

2-30. 2-31. 2-32. 2-33. 2-34. 3-1. 3-2. 3-3.

Display Operating Mode Bits . . . . . . . . . . . . . System Control Port A (Hex 0092) . . . . . . . . . System Control Port B (Hex 0061, Write) . . . . . System Control Port B (Hex 0061, Read) . . . . . Error Codes . . . . . . . . . . . . . . . . . . . . . . . BIOS Video VGA Modes . . . . . . . . . . . . . . . Video BIOS Extended Modes--NeoMagic NM2160 PCMCIA PC Card Slot Pin Assignments . . . . . .

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2-26 2-29 2-30 2-30 2-34 3-3 3-4 3-10

viii

Preface
This technical reference contains hardware and software interface information specific to the IBM ThinkPad 600 computer. This technical reference is intended for those who develop hardware and software products for the computer. Users should understand computer architecture and programming concepts. This publication consists of the following sections and appendixes: Section 1, "System Overview," describes the system, features, and specifications. Section 2, "System Board," describes the system-specific hardware implementations. Section 3, "Subsystems," describes the hardware functions specific to the ThinkPad 600 computer. Appendix A, "System Resources," describes the available system resources for the computer and docking stations. Appendix B, "System Management API (SMAPI) BIOS Overview," describes the system software interface built into the system, called the System Management Application Program Interface (SMAPI) BIOS, which controls the system information, system configuration, and power management features of the ThinkPad computer. Appendix C, "Appendix C," contains special notices and trademark information. An index is also included. Attention The term Reserved describes certain signals, bits, and registers that should not be changed. Use of reserved areas can cause compatibility problems, loss of data, or permanent damage to the hardware. When the contents of a register are changed, the state of the reserved bits must be preserved. Read the register first and change only the bits that must be changed.

Copyright IBM Corp. 1998

ix

x

Preface

Section 1. System Overview
Description . . . . . . . . . . . . . . System Board Devices and Features System Board I/O Address Map . . Specifications . . . . . . . . . . . . . Performance Specifications . . . Physical Specifications . . . . . . Electrical Specifications . . . . . Acoustical Readings . . . . . . . Power Supply . . . . . . . . . . . . . Voltages . . . . . . . . . . . . . . Output Protection . . . . . . . . . Voltage Sequencing . . . . . . . . Power Supply Connector . . . . . Battery Pack . . . . . . . . . . . . .
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1-2 1-3 1-5 1-7 1-7 1-8 1-9 1-9 1-10 1-10 1-11 1-11 1-11 1-12

Copyright IBM Corp. 1998

1-1

Description
The IBM ThinkPad 600 computer (hereafter called the ThinkPad computer or the computer) is a notebook-size computer that features AT bus architecture. Each computer supports one UltraSlim Bay and one internal hard disk drive. The ThinkPad 600 computer also supports an internal CD-ROM drive or a diskette drive in the UltraSlim Bay. Programs can distinguish the foregoing computer model from other ThinkPad models by reading the system ID: Interrupt 15H Function code (AH)=C0H. Returns ES:(BX+2) : Model Byte ES:(BX+3) : Submodel Byte The system microprocessor contains an internal cache and a cache controller. Figure 1-1 lists the model bytes, submodel bytes, and system clock speed of the system board for each model.
Model 600 Model Byte (Hex) FC Submodel Byte (Hex) 01 System Clock 33 MHz

Figure 1-1. Model and Submodel Bytes

For a listing of the other systems, refer to the IBM Personal System/2 and Personal Computer BIOS Interface.

1-2

System Overview

System Board Devices and Features
Figure 1-2 lists the system board devices and their features. The IBM Personal System/2 Hardware Interface Technical Reference describes devices common to PS/2 products by type number.
Device Microprocessor Type ­ Features Intel Pentium processor with the MMX technology 233 MHz or Intel Pentium II processor 233 or 266 MHz External cache System timers ­ 1 512 KB (write back) Channel 0: system timer Channel 1: refresh generation Channel 2: tone generator for speaker 128 KB by 4 banks (1 KB equals 1024 bytes) 32 to 160 MB (1 MB equals 1,048,576 bytes) 128 bytes CMOS RAM with real-time clock/calendar + 4 KB NVRAM 1 K bits XGA video functions: Up to 65,536 colors on the TFT XGA (1024x768) LCD and HPA XGA (1024 x 768). Up to 16,777,216 colors on an external monitor See "Video Subsystem" on page 3-2 for more details on the video subsystem. DMA controller 1 Seven DMA channels (AT compatible:) Four 8-bit channels and three 16-bit channels

ROM subsystem RAM subsystem CMOS RAM subsystem EEPROM subsystem Video subsystem

­ ­ ­ ­ ­

Figure 1-2 (Part 1 of 2). System Board Devices and Features

System Overview

1-3

Device Interrupt controller Keyboard/auxiliary device controller

Type 1 1

Features 15 levels of system interrupts (interrupts are edge-triggered) Internal keyboard TrackPoint Auxiliary device connector Password security Supports: 3.5-in. diskette (1.44 MB) 3.5-in. diskette (1.2 MB) 3.5-in. diskette (720 KB)

Diskette drive controller

2

Serial controller port Parallel controller port

2

1

Expansion bus adapter (PCI-bus)

­

EIA-232-E interface (16550 compatible) Programmable as serial port 1, 2, 3, or 4 One 9-pin, D-sub connector Programmable as parallel port 1, 2, or 3 IEEE P1284-A compatible Supports bidirectional input and output Enhanced Parallel Port (EPP) compatible Extended Capabilities Port (ECP) compatible Supports externally attached devices: SelectaDock docking system Port replicator

PCMCIA slots

­

Conforms to the standards for: CardBus Two Type I or II PC cards One Type III PC card

Modem subsystem

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Is driven by: MDSP 3780i SRAM 32 Kb by 40 bits Crystal Audio Voice band CODEC for modem Internal DAA Internal omnidirectional microphone

Infrared subsystem

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Supports: ThinkPad IR/SIR/D-ASK (500 KHz) IR

Universal serial bus (USB)

­

Supports: USB input and output devices Personal Computer Memory Card International Association

Figure 1-2 (Part 2 of 2). System Board Devices and Features

1-4

System Overview

System Board I/O Address Map
Figure 1-3 is the I/O address map.
Address (Hex) 0000­001F 0020, 0021 0022­002F 0040­0043 0048­004B 0060 0061 0062, 0066 0064 0070, 0071 0072, 0073 0074, 0075, 0076 0081­0083, 0087 0089­008B, 008F 0092 0096 0098 00A0, 00A1 00B2­00B3 00C0­00DF 00F0­00FF 0130­013F 0170­0177 01F0­01F7 0201 0220­0233 0240­0253 026E, 026F 0260­0273 0278­027A 027B­027F 0280­0283 02E8­02EF 02E8­02EF 02F8­02FF 02F8­02FF 0300­0303 0310­0313 0320­0323 Device DMA Controller (0­3) Interrupt Controller (Master) Reserved System Timer 1 Reserved Keyboard, Auxiliary Device System Control Port B Slave Controller Keyboard, Auxiliary Device RT/CMOS and NMI Mask Extended RT and CMOS Reserved DMA Page Registers (0­3) DMA Page Registers (4­7) System Control Port A Reserved System Flash ROM Control Register (DCR 2282) Interrupt Controller (Slave) Power Management Register DMA Controller (4­7) Reserved ThinkPad Modem Secondary IDE Registers Primary IDE Registers Joystick Port Audio Subsystem - Sound Blaster Audio Subsystem - Sound Blaster Super I/O Configuration Registers Audio Subsystem - Sound Blaster Parallel Port 3 Reserved Audio Subsystem - Sound Blaster Serial Port 4 IR Port 4 Serial Port 2 IR Port 2 MIDI Port 1 MIDI Port 2 MIDI Port 3

Figure 1-3 (Part 1 of 2). System Board I/O Address Map

System Overview

1-5

Address (Hex) 0330­0333 0350­035F 0376, 0377 0378­037A 037B­037F 0388­038B 0398­0399 03B4, 03B5, 03BA 03BC­03BE 03C0­03C5 03C6­03C9 03CA, 03CC, 03CE, 03CF, 03D4, 03D5, 03DA, 03D8­03DA 03E0­03E1 03E8­03EF 03E8­03EF 03F0­03F5, 03F7 03F6, 03F7 03F8­03FF 03F8­03FF 0530­0537 0538­053F 0604­060B 0770­077F 0CF8­0CFB 0CFC­0CFF 0DB0­0DBF 0D38­0D3F 0E80­0E87 0E88­0E8F 0F40­0F47 0FF0­0FF7 15E8­15EF 2120­21FF 23C0­23C7 EF00­EF37 EFA0­EFAD F104

Device MIDI Port 4 ThinkPad Modem Secondary IDE Registers Parallel Port 2 Reserved Audio Subsystem - FM Synthesizer Reserved Video Subsystem Parallel Port 1 Video Subsystem Video DAC Video Subsystem

PCMCIA Interface (DCR 2959) Serial Port 3 IR Port 3 Diskette-Drive Controller Primary IDE Registers Serial Port 1 IR Port 1 Audio - WSS 1 Audio Control Port 1 Audio - WSS 2 ThinkPad Modem PCI Configuration Address Register PCI Configuration Data Register ThinkPad Modem Audio Control Port 2 Audio - WSS 3 Audio Control Port 3 Audio - WSS 4 Audio Control Port 4 Power Management Register Reserved Reserved Power Management Register SMBus IO Space Register Reserved

Figure 1-3 (Part 2 of 2). System Board I/O Address Map

1-6

System Overview

Specifications
Figure 1-4 to Figure 1-7 list the specifications for the computers.

Performance Specifications
Device/Cycle Microprocessor L1 cache (64bit) read/write hit L2 cache (64bit) (for not all models) read hit (back-to-back) write hit (back-to-back) Memory (64bit) (see Note) read, page hit read, bank miss read, page miss posted write write retire rate from write buffer Note: Clock Counts (66 MHz) 233 or 266 MHz 1 CPUCLK 3-1-1-1(1-1-1-1)

5-1-1-1 8-1-1-1 11-1-1-1 3-1-1-1 -1-1-1

The cycle times shown for access to system board RAM are based on 66 MHz memory bus (SDRAM, CAS LATENCY=2)

Figure 1-4. Performance Specifications

System Overview

1-7

Physical Specifications
Size Width: 300.0 mm (12 in.) Depth: 240.0 / 254.0 mm (9.6 / 10.16 in.) Height: 36.5 mm (1.46 in.) Weight by model (approximate value) 21U 5.45 lb 31U 5.04 lb 41U 5.47 lb 51U 5.55 lb 61U 5.06 lb Air Temperature System on (without diskette) 5.0°C to 35.0°C (41°F to 95°F) System on (with diskette) 10.0°C to 35.0°C (50°F to 95°F) System off 5.0°C to 43.0°C (41°F to 110°F) Humidity System (without diskette) 8% to 95% System (with diskette) 8% to 80% Maximum altitude : 3,048 m (10,000 ft) in unpressurized conditions Heat output: 56 W Acoustical readings (see Figure 1-7 on page 1-9) Electrical (see Figure 1-6 on page 1-9) Electromagnetic compatibility: FCC class B With battery pack installed. This is the maximum altitude at which the specified air temperatures apply. At higher altitudes, the maximum air temperatures are lower than those specified.

Figure 1-5. Physical Specifications

1-8

System Overview

Electrical Specifications
(56 W) Input voltage (V ac) Frequency (Hz) Input (kVA) 100­240 50/60 0.13

Range is automatically selected; sine wave input is required. At maximum configuration.

Figure 1-6. Electrical Specifications

Acoustical Readings
LWAd in bels Operate 600 600 (with SelectaDock III) Notes: LWAd LpAm m Operate Is the declared sound power level for the random sample of machines. Is the mean value of the A-weighted sound pressure levels at the operator position (if any) for the random sample of machines. Is the mean value of the A-weighted sound pressure levels at the 1 meter position for the random sample of machines. Shows the value while using the hard disk drive. 4.40 4.60 Idle 3.90 4.30 LpAm in dB Operate 35.0 37.5 Idle 30.0 34.0 m in dB Operate 30.0 31.0 Idle 25.5 28.0

All measurements made in accordance with ANSI S12.10 and reported in conformance with ISO 9296.

Figure 1-7. Acoustical Readings

System Overview

1-9

Power Supply
The power supply converts the ac voltage to dc voltage and provides power for the following: System board set Diskette drive Hard disk drive CD-ROM drive Auxiliary devices Keyboard LCD panel PCMCIA cards

Voltages
The power supply generates six different dc voltages: VCC5M, VCC3M, VCC12, and VCCSW. Figure 1-8 shows the maximum current for each voltage.
Output VCC5M VCC3M VCC12 VCCSW Voltage (V dc) +5.0 +3.3 +12.0 +5.0 Current (A) 5.0 5.0 0.50 0.006

Figure 1-8. Power Supply Maximum Current

1-10

System Overview

Output Protection
A short circuit placed on any dc output (between two outputs or between an output and a dc return) latches all dc outputs into a shutdown state, with no hazardous condition to the power supply. If an overvoltage fault occurs in the power supply, the power supply latches all dc outputs into a shutdown state before any output exceeds 135% of the nominal value of the power supply.

Voltage Sequencing
When power is turned on, the output voltages reach their operational voltages within 2 seconds.

Power Supply Connector
The following connector is used with the AC Adapter. The total power capacity of this connector must not exceed 4.0 A.

Refer to Figure 1-9 for the appropriate adapter pin assignments.
Pin 1 2 Voltage +7.0 V dc to +17.0 V dc (depending on charging conditions) Ground

Figure 1-9. Voltage Pin Assignments for the 56W AC Adapter

System Overview

1-11

Battery Pack
The ThinkPad computer uses a lithium-ion (Li-ion) battery pack that meets the following electrical specifications:
Nominal Voltage Capacity (average) Protection +10.8 V dc 3.2 ampere hours (AH) Overcurrent protection Overvoltage protection Overdischarge protection Thermal protection

Figure 1-10. Lithium-Ion Battery Pack Specifications

1-12

System Overview

Section 2. System Board
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . Cache Memory Operation . . . . . . . . . . . . . . . . . . Cacheable Address Space . . . . . . . . . . . . . . . . . . Bus Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard/Mouse Connector . . . . . . . . . . . . . . . . . . . Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . Scan Codes . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard ID . . . . . . . . . . . . . . . . . . . . . . . . . . Displayable Characters and Symbols . . . . . . . . . . . . Hard Disk Drive Connector . . . . . . . . . . . . . . . . . . . External Bus Connector . . . . . . . . . . . . . . . . . . . . . UltraSlim Bay Connector . . . . . . . . . . . . . . . . . . . . Diskette Drive and Controller . . . . . . . . . . . . . . . . . . Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ROM Subsystem . . . . . . . . . . . . . . . . . . . . . . . RAM Subsystem . . . . . . . . . . . . . . . . . . . . . . . . System Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . System Board Memory for the DIMM Connectors RT/CMOS RAM . . . . . . . . . . . . . . . . . . . . . . . . RT/CMOS Address and NMI Mask Register (Hex 0070) RT/CMOS Data Register (Hex 0071) . . . . . . . . . . RT/CMOS RAM I/O Operations . . . . . . . . . . . . . CMOS RAM Configuration . . . . . . . . . . . . . . . . Miscellaneous System Functions and Ports . . . . . . . . . Nonmaskable Interrupt (NMI) . . . . . . . . . . . . . . . . System Control Port A (Hex 0092) . . . . . . . . . . . . . System Control Port B (Hex 0061) . . . . . . . . . . . . . Power-On Password . . . . . . . . . . . . . . . . . . . . . Other Passwords . . . . . . . . . . . . . . . . . . . . . . . Selectable Drive-Startup Sequence . . . . . . . . . . . . . Hardware Compatibility . . . . . . . . . . . . . . . . . . . . . Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-2 2-2 2-2 2-3 2-3 2-4 2-4 2-4 2-4 2-6 2-7 2-8 2-8 2-11 2-14 2-15 2-15 2-15 2-16 2-17 2-18 2-19 2-19 2-20 2-24 2-28 2-28 2-29 2-30 2-31 2-31 2-32 2-33 2-34

Copyright IBM Corp. 1998

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Description
This section describes the microprocessor, connectors, memory subsystems, and miscellaneous system functions and ports for the ThinkPad 600 computer.

Microprocessor
The ThinkPad 600 uses the Intel Pentium II 233 MHz processor with MMX technology or the Intel Pentium 233 or 266 MHz processor. The processor has a 32-bit address bus and a 64-bit data bus. It is software-compatible with all previous microprocessors. The processor has an internal, split data and instruction, 32-KB write-back cache. It includes pipelined math coprocessor functions and superscalar architecture (two execution units).

Cache Memory Operation
In addition to the 32 KB of internal Level 1 (L1) cache memory in the microprocessor, the system board of the ThinkPad 600 computer contains an additional 512 KB of external Level 2 (L2) cache memory. The cache memory in the Intel Pentium II microprocessor and the L2 external cache memory enable the microprocessor to read instructions and data much faster than if the microprocessor had to access system memory. When an instruction is first used or data is first read or written, it is transferred to the cache memory from main memory. This enables future accesses to the instructions or data to occur much faster. The cache is disabled and empty when the microprocessor comes out of the reset state. The cache is tested and enabled during the power-on self-test (POST). The cache memory in the Intel Pentium II microprocessor is loaded from system memory in 32-byte increments, each referred to as a cache line. A cache line is aligned on a paragraph boundary. A reference to any byte contained in a cache line results in the entire line being read into the cache memory (if the data was not already in the cache). When the microprocessor gives up control of the system

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System Board

bus, the cache memory enters "snoop" mode and monitors all write and read operations. If memory data is written to a location in the cache and the cache line is in the "modified" state, the corresponding cache line is written back to system memory and invalidated. When the microprocessor performs a memory read, the data address is used to find the data in the cache. If the data is found (a hit), it is read from the cache memory and no external bus cycle occurs. If the data is not found (a miss), an external bus cycle is used to read the data from system memory. If the address of the missed data is in cacheable address space, the data is stored in the cache memory and the remainder of the cache line is read. When the microprocessor performs a memory write, the data address is used to search the cache. If the address is found (a hit), the data is written to the cache and no external bus cycle is used to write the data to system memory. (If the address of the write operation was not in the cache memory but was in cacheable address space, the data is read back into the cache memory and the remainder of the cache line is read.)

Cacheable Address Space
Cacheable address space is defined as system memory that resides on the system board (0­640 KB and 1 MB­256 MB). Cacheability of system memory is up to 64 MB for Pentium or 512 MB for Pentium II in the L2 cache. Nothing in address range hex A0000­BFFFF, I/O address space, or memory in any AT slot is cached. ROM address space (hex C0000­C9FFF and F0000­FFFFF) is L1 cacheable for code read operations only. If data in this address range is already in cache memory and the address range is written to, the cached line is invalidated and is read again from RAM, where the BIOS is shadowed.

Bus Adapter
When the computer is attached to the ThinkPad SelectaDock III docking system, the PCI adapters or AT-bus adapters can be used through the docking system.

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Keyboard/Mouse Connector
Each ThinkPad computer has a keyboard/mouse connector, where the IBM mouse, keyboard, or numeric keypad is connected.

Signals
The keyboard and mouse signals are driven by open-collector drivers pulled to 5 V dc through a pull-up resistor. Figure 2-1 lists the signals.
Sink current High-level output voltage Low-level output voltage High-level input voltage Low-level input voltage 1 mA 5.0 V 0.5 V 2.0 V 0.8 V dc minus pullup dc dc dc Maximum Minimum Maximum Minimum Maximum

Figure 2-1. Keyboard and Mouse Signals

Connector
The keyboard/mouse connector uses a 6-pin, miniature DIN connector.
6 4 2 1 5 3

Pin 1 2 3 4 5 6

I/O I/O I/O ­ ­ I/O I/O

Signal Name Mouse Data Keyboard Data Ground +5 V dc Mouse Clock Keyboard Clock

Figure 2-2. Keyboard/Mouse Connector Pin Assignments

Note: The maximum current for +5 V dc (pin 4) is 0.5 A.

Scan Codes
Figure 2-3 shows the key numbers assigned to keys on the 85-key keyboard (for the U.S.).

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System Board

Figure 2-3. Key Numbers for the 85-Key Keyboard

Figure 2-4 shows the key numbers assigned to keys on the 86-key keyboard (for countries other than the U.S.and Japan).

Figure 2-4. Key Numbers for the 86-Key Keyboard

Figure 2-5 on page 2-6 shows the key numbers assigned to the keys on the 90-key keyboard (for Japan).

System Board

2-5

Figure 2-5. Key Numbers for the 90-Key Keyboard

For scan codes assigned to each numbered key, refer to the IBM Personal System/2 Hardware Interface Technical Reference.

Keyboard ID
The keyboard ID consists of 2 bytes: hex 83AB (the built-in keyboard with the external numeric keypad) or hex 84AB (the built-in keyboard only). Interrupt 16H, function code (AH)=0AH, returns the keyboard ID in BX.

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System Board

Figure 2-6 shows the key numbers assigned to keys on the external numeric keypad. For scan codes assigned to each numbered key, refer to the IBM Personal System/2 Hardware Interface Technical Reference.
90 95 100 105

91

96

101 106

92

97

102

93

98

103 108

99

104

Figure 2-6. Key Numbers for the External Numeric Keypad

Displayable Characters and Symbols
For displayable characters and symbols that are keyable from the keyboard, refer to the IBM Personal System/2 Hardware Interface Technical Reference.

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Hard Disk Drive Connector
The hard disk drive connected to the system board is removable. Figure 2-7 shows the pin assignments for the connector on the system board.

Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43

Signal

I/O or Feature

Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44

Signal GND PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 Key GND GND GND CSEL(GND) GND Reserved -PDIAGHDD PDA2 -CS3P GND VCC5B Reserved

I/O or Feature Ground I/O I/O I/O I/O I/O I/O I/O I/O NC Ground Ground Ground 0 Ground NC I O O Ground Vcc NC

RSTDRVI O PDD7 I/O PDD6 I/O PDD5 I/O PDD4 I/O PDD3 O PDD2 I/0 PDD1 I/O PDD0 I/O GND Ground -PDREQ I -PDIOW O -PDIOR O PIODRY I -PDACK O IRQ14 I PDA1 O PDAO O -CS1P Ground -DASPHDD2 I VCC5B Vcc GND Ground

Figure 2-7. Hard Disk Drive Connector Pin Assignments

External Bus Connector
The docking station is connected through the 240-pin external bus connector on the rear panel. This connector is installed on the system board and has the following pin assignments:
121 1

60

180

240

120

61 181

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Pin 001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 016 017 018 019 020 021 022 023 024 025 026 027 028 029 030 031 032 033 034 035 036 037 038 039 040 041 042 043 044 045 046 047 048 049 050 051 052 053 054 055 056 057 058 059 060 VCC5A VCC5A -PCIRST_DOCK -ACK_DOCK -CLKRUN_DOCK GND GND AD30 AD28 AD26 AD24 GND GND AD23 AD21 AD19 AD17 GND GND C_BE2 -IRDY_DOCK -DEVSEL_DOCK -LOCK_DOCK GND GND -SERR_DOCK -PAR_DOCK TDO TMS -TRST -BRRESET AD14 AD12 AD10 AD8 GND GND AD7 AD5 AD3 GND GND AD1 PRDY -CPURST_DS -IODCD IOTXD -IORTS -IODSR SAFE5V XKBCLK GND GND DODK_R_IN AGND DOCK_R_OUT DOCK-PWR DOCK-PWR DOCK-PWR DOCK-PWR

Signal Name 061 062 063 064 065 066 067 068 069 070 071 072 073 074 075 076 077 078 079 080 081 082 083 084 085 086 087 088 089 090 091 092 093 094 095 096 097 098 099 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120

Pin Dock-PWR Dock-PWR Dock-PWR Dock-PWR DOCK-L_OUT AGND DOCK-L_IN XKBDATA GND GND MSDATA MSCLK -TORI -IOCTS -IODTR -IORXD -PWRON AD0 AD2 GND GND AD4 AD6 C_BE0 GND AD9 AD11 AD13 R_-S -MOTENO TCLK TDI AD15 C_BE1 -PERR_DOCK -STOP DOCK -TRDY_DOCK GND GND -FRAME_DOCK GND AD16 AD18 GND AD20 GND AD22 C_BE3 GND GND AD25 AD27 AD29 AD31 GND -REQ_DOCK PCICLK_DOCK -BATOPDSBL VCC5B VCC5B

Signal Name

Figure 2-8 (Part 1 of 2). 240-Pin External Bus Connector Pin Assignments

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Pin 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 GND -DOCK_ID1 IRQSER IRQ5 IRQ7 IRQ10 IRQ11 IRQ14 -INTB_DOCK -INTC_DOCK -INTD_DOCK -DASPDOCK GND GND CRTID0 CDTID2 DDCCLK_ID3 GND CRT_RED LPTSLCT LPTPE LPTBUSY LPTD7 LPTD6 LPTD3 LPTD2 LPTD1 LPTD0 -LPTAFD GND GND GND -LPTERR -WRDATA_1 -DRVSEL1 -DRVIDO -MEDID0 DRATE1 -STEP GND -MEDID1 -TRACK0 -WPROTECT GND GND LAST_PWG -EVENT DOCK_SPKR JAB1 JAB2 JACX JACY 12C_CLK GND GND SUSCLK -PCIPME USB_OC1 GND -DOCK_ID3

Signal Name 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240

Pin -DOCK_ID2 GND USBP1UDBP1+ GND GND 12C_DATA JBCY JBCX JBB2 VTTON JBB1 MIDIOUT_DOCK MIDIIN_DOCK GND GND -PWRSWITCH -BUSSUSSTAT -PCMCIARI4 -SIDE1SEL DRATE0 -WREN -DRVID1 -DIR -MOTEN1 GND -DISKCHG -INDEX_1 -PDDATA_1 GND GND -LPTSTB -LPTINIT -LPTSLIN LPTD4 LPTD5 GND GND -LPTACK GND CRT_GREEN GND CRT_BLUE DDCDATA_ID1 CRT_VSYNC_EXT CRT_HSYNC_EXT GND GND -PHLDA_DOCK -PHLD_DOCK -INTA_DOCK IDE2IRQ IRQ15 IRQ12 IRQ9 IRQ6 IRQ4 IRQ3 GND -DOCK_ID0

Signal Name

Figure 2-8 (Part 2 of 2). 240-Pin External Bus Connector Pin Assignments

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System Board

UltraSlim Bay Connector
The removable diskette drive or CD-ROM drive can be connected to the UltraSlim Bay connector on the system board. This connector has the following pin assignments.

System Board

2-11

Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Signal -UBAYID1 -UBAYID2 GND GND -INDEX -DRVSEL0 -DISKCHG -DRVID0 NC -MEDID0 -MONTEN0 DRATE1 -DIR -DRVID1 -STEP GND -WRDATA GND -WREN -MEDID1 -TRACK0 DRATE0 -WPROTECT -RDDATA GND -SIDE1SEL -UBAYID0 BAYRESET GND SDD7 SDD8 SDD6 SDD9 GND SDD5 DD10 SDD4 SDD11 VCC5B VCC5B VCC5B VCC5B SDD3 SDD12 SDD2 SDD13 GND SDD1 SDD14 SDD0

I/O and Feature I I GND GND I O I I N/C I O O O I 0 GND O GND O I I O I I GND O O O GND I/O I/O I/O I/O GND I/O I/O I/O I/O VCC VCC VCC VCC I/O I/O I/O I/O GND I/O I/O I/O

Figure 2-9 (Part 1 of 2). UltraSlim Bay Connector Pin Assignments

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System Board

Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

Signal SDD15 GND UBAYID0 -SDREQ GND -SDIOW GND -SDIOR GND SIORDY UBAYSLAVE -SDACK IRQ Reserved SDA1 -PDIAGHDD SDA0 SDA2 -CS1S -CS3S -DASPUBAY -MCS CD_MUTE AUDIO_RTN CD_L_IN CD_R_IN GND GND -UBAYID3 -UBAYID4

I/O and Feature I/O GND I I GND O GND O GND I O O I I O I/O O O O O I O I I I I GND GND I I

Figure 2-9 (Part 2 of 2). UltraSlim Bay Connector Pin Assignments

System Board

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Diskette Drive and Controller
Figure 2-10 shows the read, write, and format capabilities of the diskette drive for the ThinkPad computer.
Format Size Diskette Type 3.5-inch 1.0 MB Diskette 3.5-inch 2.0 MB Diskette Legend: : 1 KB (kilobyte) 1 MB (megabyte) R W F 1024 bytes 1,048,576 bytes Read Write Format 720 KB RWF - 1.2 MB - RWF 1.44 MB - RWF

Figure 2-10. Diskette Drive Read, Write, and Format Capabilities

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System Board

Memory
The ThinkPad computers use the following types of memory: Read-only memory (ROM) Random access memory (RAM) Real-time clock/complementary metal-oxide semiconductor RAM (RT/CMOS RAM)

ROM Subsystem
The ROM subsystem consists of four banks of 128-KB memory. ROM is active when power is turned on and is assigned to the top of the first and last 1 MB of address space (hex 000F0000­000FFFFF and hex FFFF0000­FFFFFFFF). After POST checks that system memory is operating correctly, the ROM code is copied to RAM at the same address space, and ROM is disabled.

RAM Subsystem
The RAM subsystem on the system board starts at address hex 00000000 of the address space. The RAM subsystem for the ThinkPad 600 computer is 64 bits wide. The 32-MB base memory is on the system board. Two 144-pin 8-byte dual inline memory module (DIMM) connectors are provided on the system board. Both connectors accept an 8-MB, a 16-MB, a 32-MB, or a 64-MB DIMM. The memory capacity can be increased up to 160 MB. The total amount of usable memory is less than the amount of memory installed because of ROM-to-RAM remapping and power management.

System Board

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System Memory Map
Memory is mapped by the memory controller registers. Figure 2-11 shows the memory map for a correctly functioning system. Memory can be mapped differently if POST detects an error in system board memory or RT/CMOS RAM. In the figure, the variable x represents the number of 1-MB blocks of system board memory starting at or above the hex 100000 boundary.
Hex Address Range 00000000 to 0009FFFF 000A0000 to 000BFFFF 000C0000 to 000C9FFF 000C8000 to 000EFFFF 000F0000 to 000FFFFF 00100000 to (00100000 + x MB) FFFF0000 to FFFFFFFF Function 640-KB system board RAM Video RAM System board video BIOS ROM mapped to RAM Channel ROM 64-KB system board ROM mapped to RAM

x MB system board RAM
64-KB system board ROM (same as 000F0000 to 000FFFFF)

Figure 2-11. System Memory Map

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System Board

System Board Memory for the DIMM Connectors
The system board has two DIMM connectors. Figure 2-12 shows the pin assignments for the DIMM connector.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Signal Vss Vss DQ0 DQ32 DQ1 DQ33 DQ2 DQ34 DQ3 DQ35 Vcc Vcc DQ4 DQ36 DQ5 DQ37 DQ6 DQ38 DQ7 D39 Vss Vss DQMB0 DQMB4 DQMB1 DQMB5 Vcc Vcc A0 A3 A1 A4 A2 A5 Vss Vss DQ8 Pin 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 Signal DQ40 DQ9 DQ41 DQ10 DQ42 DQ11 DQ43 Vcc Vcc DQ12 DQ44 DQ13 DQ45 DQ14 DQ46 DQ15 DQ47 Vss Vss Reserved Reserved Reserved Reserved CK0 CKEA Vcc Vcc /RAS /CAS /WE CKEB /S0 CKEB /S1 RFU RFU CK1 Pin 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 Signal Vss Vss Reserved Reserved Reserved Reserved Vcc Vcc DQ16 DQ48 DQ17 DQ49 DQ18 DQ50 DQ19 DQ51 Vss Vss DQ20 DQ52 DQ21 DQ53 DQ22 DQ54 DQ23 DQ55 Vcc Vcc A6 A7 A8 A11 (BS0) Vss Vss A9 Pin 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Signal A12 (BS1) A10 (AP) A13 Vcc Vcc DQMB2 DQMB6 DQMB3 DQMB7 Vss Vss DQ24 DQ56 DQ25 DQ57 DQ26 DQ58 DQ27 DQ59 Vcc Vcc DQ28 DQ60 DQ29 DQ61 DQ30 DQ62 DQ31 DQ63 Vss Vss SDA SCL Vcc Vcc

Figure 2-12. DIMM Adapter Card Memory Connector Pin Assignments

System Board

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RT/CMOS RAM
The RT/CMOS RAM (real-time clock/complementary metal-oxide semiconductor RAM) module contains the real-time clock and 128 bytes of CMOS RAM. The clock circuitry uses 14 bytes of this memory; the remainder is allocated to configuration and system-status information. A battery is built into the module to keep the RT/CMOS RAM active when the power supply is not turned on. In addition to the 128 bytes of CMOS/RAM, a CMOS/RAM extension of 4 KB is provided for configuration and other system information. Figure 2-13 lists the RT/CMOS RAM bytes and their addresses.
Address (Hex) 000­00D 00E 00F 010 011 012 013 014 015, 016 017, 018 019 01A 01B 01C 01D­02D 02E, 02F 030, 031 032 033­07F RT/CMOS RAM Bytes Real-time clock Diagnostic status Shutdown status Diskette drive type Hard disk 2 and 3 drive type Hard disk 0 and 1 drive type Reserved Equipment Low and high base memory Low and high expansion memory Hard disk 0 extended byte Hard disk 1 extended byte Hard disk 2 extended byte Hard disk 3 extended byte Reserved Checksum Low and high usable memory above 1 MB Date-century Reserved

Figure 2-13. RT/CMOS RAM Address Map

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System Board

RT/CMOS Address and NMI Mask Register (Hex 0070) The NMI mask register is used with the RT/CMOS data register (hex 0071) to read from and write to the RT/CMOS RAM bytes. Attention The operation following a write to hex 0070 should access hex 0071; otherwise, intermittent failures of the RT/CMOS RAM can occur.
Bit 7 6­0 Function NMI mask RT/CMOS RAM address

Figure 2-14. RT/CMOS Address and NMI Mask Register (Hex 0070)

Bit 7 Bits 6­0

When this write-only bit is set to 1, the NMI is masked (disabled). This bit is set to 1 by a power-on reset. These bits are used to select RT/CMOS RAM addresses.

RT/CMOS Data Register (Hex 0071) The RT/CMOS data register is used with the RT/CMOS address and NMI mask register (hex 0070) to read from and write to the RT/CMOS RAM bytes.
Bit 7­0 Function RT/CMOS data

Figure 2-15. RT/CMOS Data Register (Hex 0071)

System Board

2-19

RT/CMOS RAM I/O Operations During I/O operations to the RT/CMOS RAM addresses, you should mask interrupts to prevent other interrupt routines from changing the RT/CMOS address register before data is read or written. After I/O operations, you should leave the RT/CMOS address and NMI mask register (hex 0070) pointing to status register D (hex 00D). Attention The operation following a write to hex 0070 should access hex 0071; otherwise, intermittent failures of the RT/CMOS RAM can occur. Writing to the RT/CMOS RAM requires the following: 1. Write the RT/CMOS RAM address to the RT/CMOS address and NMI mask register (hex 0070). 2. Write the data to the RT/CMOS data register (hex 0071). 3. Write the address, hex 0F, to the RT/CMOS and NMI mask register; this leaves hex 0070 pointing to the shutdown status byte (hex 0F). 4. Read address hex 0071 to restore the RT/CMOS. Reading from the RT/CMOS RAM requires the following steps: 1. Write the RT/CMOS RAM address to the RT/CMOS and NMI mask register (hex 0070). 2. Read the data from the RT/CMOS data register (hex 0071). 3. Write the address, hex 0F, to the RT/CMOS and NMI mask register; this leaves hex 0070 pointing to the shutdown status byte (hex 0F). 4. Read address hex 0071 to restore the RT/CMOS.

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System Board

Real-Time Clock Bytes (Hex 000­00D): Bit definitions and addresses for the real-time clock bytes are shown in Figure 2-16.
Address (Hex) 000 001 002 003 004 005 006 007 008 009 00A 00B 00C 00D Function Seconds Second alarm Minutes Minute alarm Hours Hour alarm Day of week Date of month Month Year Status register Status register Status register Status register Byte Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13

A B C D

Figure 2-16. Real-Time Clock Bytes (Hex 000­00D)

Note: The setup program initializes status registers A and B when the time and date are set. Interrupt 1AH is the BIOS interface to read and set the time and date; it initializes the registers in the same way that the setup program does.

Status Register A (Hex 00A)
Bit 7 6-4 3­0 Function Update in progress (UIP) Division Chain Select (DVx) Rate-selection bits

Figure 2-17. Status Register A (Hex 00A)

Bit 7

This bit is a status flag that can be monitored. If this bit is 1, the update transfer will soon occur. If this bit 0, the update transfer will not occur for at least 244 µs. These bits control the divider chain for the oscillator. These bits allow the selection of a divider output frequency or disable the divider output.

Bits 6­4 Bits 3­0

System Board

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Status Register B (Hex 00B)
Bit 7 6 5 4 3 2 1 0 Function Set Enable periodic interrupt Enable alarm interrupt Enable update-ended interrupt Enable square wave Date mode 24-hour mode Enable daylight-saving time

Figure 2-18. Status Register B (Hex 00B)

Bit 7

If set to 0, this bit updates the cycle, normally by advancing the count at a rate of one cycle per second. If set to 1, it immediately ends any update cycle in progress, and the program can initialize the 14 time bytes without any further updates occurring until this bit is set to 0. This is a read/write bit that allows an interrupt to occur at a rate specified by the rate and divider bits in status register A. If set to 1, this bit enables the interrupt. The system initializes this bit to 0. If set to 1, this bit enables the alarm interrupt. The system initializes this bit to 0. If set to 1, this bit enables the update-ended interrupt. The system initializes this bit to 0. If set to 1, this bit enables the square-wave frequency as set by the rate-selection bits in status register A. The system initializes this bit to 0. This bit indicates whether the binary-coded-decimal (BCD) or binary format is used for time-and-date calendar updates. If set to 1, this bit indicates binary format. The system initializes this bit to 0. This bit indicates whether the hours byte is in 12-hour or 24-hour mode. If set to 1, this bit indicates the 24-hour mode. The system initializes this bit to 1. If set to 1, this bit enables the daylight-saving-time mode. If set to 0, this bit disables the daylight-saving-time mode, and the clock reverts to standard time. The system initializes this bit to 0.

Bit 6

Bit 5 Bit 4 Bit 3

Bit 2

Bit 1

Bit 0

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System Board

Status Register C (Hex 00C)
Bit 7 6 5 4 3­0 Function Interrupt request flag Periodic interrupt flag Alarm interrupt flag Update-ended interrupt flag Reserved

Figure 2-19. Status Register C (Hex 00C)

Note: Interrupts are enabled by bits 6, 5, and 4 in status register B. Bit 7 Bit 6 Bit 5 Bit 4 Bits 3­0 If set to 1, this bit indicates that an interrupt has occurred; bits 6, 5, and 4 indicate the type of interrupt. If set to 1, this bit indicates that a periodic interrupt has occurred. If set to 1, this bit indicates that an alarm interrupt has occurred. If set to 1, this bit indicates that an update-ended interrupt has occurred. These bits are reserved.

Status Register D (Hex 00D)
Bit 7 6­0 Function Valid RAM Reserved

Figure 2-20. Status Register D (Hex 00D)

Bit 7

This read-only bit monitors the internal battery. If set to 1, this bit indicates that the real-time clock has power. If set to 0, it indicates that the real-time clock has lost power and the data in CMOS is no longer valid. These bits are reserved.

Bits 6­0

System Board

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CMOS RAM Configuration Figure 2-21 shows the bit definitions for the CMOS RAM configuration bytes.

Diagnostic Status Byte (Hex 00E)
Bit 7 6 5 4 3 2 1, 0 Function Real-time clock power Configuration record and checksum status Incorrect configuration Memory size mismatch Hard disk controller/drive C initialization status Time status indicator Reserved

Figure 2-21. Diagnostic Status Byte (Hex 00E)

Bit 7 Bit 6 Bit 5

If set to 1, this bit indicates that the real-time clock has lost power. If set to 1, this bit indicates that the checksum is incorrect. This bit indicates the results of a power-on check of the equipment byte (hex 014). If set to 1, this bit indicates that the configuration information is incorrect. If set to 1, this bit indicates that the memory size does not match the configuration information. If set to 1, this bit indicates that the controller or hard disk drive failed initialization. If set to 1, this bit indicates that the time is invalid. These bits are reserved.

Bit 4 Bit 3 Bit 2 Bits 1, 0

Shutdown Status Byte (Hex 00F): This byte is defined by the power-on diagnostic programs.

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Diskette Drive Type Byte (Hex 010): This byte indicates the type of the installed diskette drive.
Bit 7­4 3­0 Drive Type Diskette drive type Reserved

Figure 2-22. Diskette Drive Type Byte (Hex 010)

Bits 7­4

These bits indicate the diskette drive type.
Description

Bits 7­4

0110 Diskette drive (2.88MB) 0100 Diskette drive (1.44MB) Note: Combinations not shown are reserved.

Figure 2-23. Diskette Drive Type Bits 7­4

Bits 3­0

These bits are reserved.

Hard Disk Drive Type Byte (Hex 011): This byte defines the type of hard disk drive installed. Hex 00 indicates that no hard disk drive is installed.

Bit 7­4 3­0

Drive Type Hard disk drive type 2 Hard disk drive type 3

Figure 2-24. Hard Disk Type Byte (Hex 011)
Bit 7­4 0000 1111 Description No drive installed for hard disk drive 2 Use CMOS 1BH for hard disk drive 2

Figure 2-25. Hard Disk Drive Type 2 (Bits 7­4)

Bit 3­0 0000 1111

Description No drive installed for hard disk drive 3 Use CMOS 1CH for hard disk drive 3

Figure 2-26. Hard Disk Drive Type 3 (Bits 3­0)

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Hard Disk Drive Type Byte (Hex 012): This byte defines the type of hard disk drive installed. Hex 00 indicates that no hard disk drive is installed.
Bit 7­4 3­0 Drive Type Hard disk drive 0 Hard disk drive 1

Figure 2-27. Hard Disk Drive Type Byte

Reserved Bytes (Hex 013): These bytes are reserved. Equipment Byte (Hex 014): This byte defines the basic equipment in the system for the power-on diagnostic tests.
Bit 7, 6 5, 4 3, 2 1 0 Description Number of diskette drives Display operating mode Reserved Coprocessor presence Diskette drive 0 presence

Figure 2-28. Equipment Byte

Bits 7, 6

These bits indicate the number of installed diskette drives.
Number of Diskette Drives One drive Reserved Reserved Reserved

Bits 7,6 0 0 1 1 0 1 0 1

Figure 2-29. Installed Diskette Drive Bits

Bits 5, 4

These bits indicate the operating mode of the display attached to the video port.
Display Operating Mode Reserved 40-column mode 80-column mode Monochrome mode

Bits 5,4 0 0 1 1 0 1 0 1

Figure 2-30. Display Operating Mode Bits

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Bits 3­2 Bit 1 Bit 0

These bits are reserved. If set to 1, this bit indicates that a coprocessor is installed. If set to 1, this bit indicates that physical diskette drive 0 is installed.

Low and High Base Memory Bytes (Hex 015 and Hex 016): The low and high base memory bytes define the amount of memory below the 640-KB address space.
The value in these bytes represents the number of 1-KB blocks of base memory. For example, hex 0280 indicates 640 KB. The low byte is hex 015; the high byte is hex 016.

Low and High Expansion Memory Bytes (Hex 017 and Hex 018): The low and high expansion memory bytes define the amount of memory above the 1-MB address space.
The value in these bytes represents the number of 1-KB blocks of expansion memory. For example, hex 0800 indicates 2048 KB. The low byte is hex 017; the high byte is hex 018.

Reserved Bytes (Hex 01D­02D): These bytes are reserved. Configuration Checksum Bytes (Hex 02E and Hex 02F): The configuration checksum bytes contain the checksum character for bytes hex 010 through hex 02D of the 64-byte CMOS RAM. The high byte is hex 02E; the low byte is hex 02F. Low and High Usable Memory Bytes (Hex 030 and Hex 031): The low and high usable memory bytes define the total amount of contiguous memory from 1 MB to 20 MB.
The hexadecimal values in these bytes represent the number of 1-KB blocks of usable memory. For example, hex 0800 is equal to 2048 KB. The low byte is hex 30; the high byte is hex 31.

Date-Century Byte (Hex 032): Bits 7 through 0 of the date-century byte contain the binary-coded decimal value for the century. For information about reading and setting this byte, refer to the IBM Personal System/2 and Personal Computer BIOS Interface. Reserved Bytes (Hex 033­07F): These bytes are reserved.

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Miscellaneous System Functions and Ports
This section provides information about nonmaskable interrupts (NMIs), the power-on password, and hardware compatibility.

Nonmaskable Interrupt (NMI)
The NMI signals the system microprocessor that a channel check timeout has occurred. This situation can cause lost data or an overrun error on some I/O devices. The NMI masks all other interrupts. The interrupt return (IRET) instruction restores the interrupt flag to the state it was in before the interrupt occurred. A system reset causes a reset of the NMI. The NMI requests from a system board channel check are subject to mask control with the NMI mask bit in the RT/CMOS Address register. See "RT/CMOS Address and NMI Mask Register (Hex 0070)" on page 2-19. The power-on default of the NMI mask is 1 (NMI disabled). Attention The operation following a write to hex 0070 should access hex 0071; otherwise, intermittent failures of the RT/CMOS RAM can occur.

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System Control Port A (Hex 0092)
Bit 7­4 3 2 1 0 Function Reserved Security lock latch Reserved (must be set to 0) Alternate gate A20 Alternate hot reset

Figure 2-31. System Control Port A (Hex 0092)

Bits 7­4 Bit 3

These bits are reserved. This bit provides a security lock for the secured area of RT/CMOS. If this bit is set to 1, the 8-byte power-on password is locked by the software. After this bit is set by POST, it can be cleared only by turning the system off. This bit is reserved. This bit is used to enable the `address 20' signal (A20) when the microprocessor is in the real address mode. If this bit is set to 0, A20 cannot be used in real mode addressing. This bit is set to 0 during a system reset. This bit provides an alternative method of resetting the system microprocessor. This alternative method supports operating systems requiring faster operation than that provided on the IBM Personal Computer AT. Resetting the system microprocessor switches the microprocessor from protected mode to real address mode. This bit is set to 0 by either a system reset or a write operation. If a write operation changes this bit from 0 to 1, the `processor reset' signal is pulsed after the reset has occurred. While the reset is occurring, the latch remains set so that POST can read this bit. If the bit is set to 0, POST assumes that the system was just powered on. If the bit is set to 1, POST assumes that the microprocessor has been switched from protected mode to real mode. If bit 0 is used to reset the system microprocessor to the real mode, use the following procedure: 1. Disable all maskable and nonmaskable interrupts.

Bit 2 Bit 1

Bit 0

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2. Reset the system microprocessor by writing a 1 to bit 0. 3. Issue a Halt instruction to the system microprocessor. 4. Reenable all maskable and nonmaskable interrupts. If you do not follow this procedure, the results are unpredictable. Note: Whenever possible, use BIOS as an interface to reset the system microprocessor to the real mode. For more information about resetting the system microprocessor, refer to the IBM Personal System/2 and Personal Computer BIOS Interface.

System Control Port B (Hex 0061)
Bit definitions for the write and read functions of this port are shown in the following figures:
Bit 7­4 3 2 1 0 Function Reserved Enable channel check Enable PCI SERR# Enable speaker data Timer 2 gate to speaker

Figure 2-32. System Control Port B (Hex 0061, Write)

Bit 7 6 5 4 3 2 1 0

Function PCI SERR# (PCI error) status Channel check status Timer 2 output Toggles with each refresh request Enable channel check Enable PCI SERR# (PCI error) check Enable speaker data Timer 2 gate to speaker

Figure 2-33. System Control Port B (Hex 0061, Read)

Bit 7

If a system board error occurs and the PCI SERR# line is activated, this bit is set to 1.

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Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

If set to 1, this bit indicates that a channel check has occurred. If read, this bit indicates the condition of the timer/counter 2 `output' signal. If read, this bit toggles for each refresh request. If set to 0, this bit enables the channel check. This bit is set to 1 during a power-on reset. If set to 0, this bit enables the PCI SERR#. If set to 1, this bit enables the speaker data. If set to 1, this bit enables the timer 2 gate.

Power-On Password
RT/CMOS RAM has 8 bytes reserved for the power-on password and the check character. The 8 bytes are initialized to hex 00. The microprocessor can access these bytes only during POST. After POST is completed, if a power-on password is installed, the password bytes are locked and cannot be accessed by any program. During power-on password installation, the password (1 to 7 characters) is stored in the security space. Installing the password is a function of the built-in system program Easy-Setup. The power-on password does not appear on the screen when it is installed, changed, or removed. After the power-on password has been installed, it can be changed or removed only during POST. The computer also can have a keyboard password. For more information, see the keyboard and auxiliary device controller section of the IBM Personal System/2 Hardware Interface Technical Reference.

Other Passwords
In addition to the power-on password, the computer provides two more passwords: The hard-disk password (HDP) protects the data on your removable hard disk drive from being accessed by unauthorized persons.

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The supervisor password protects the system information in Easy-Setup from being changed by unauthorized persons. For more information about these passwords, refer to the ThinkPad User's Guide.

Selectable Drive-Startup Sequence
Selectable drive-startup (selectable boot) allows you to control the startup sequence of the drives in your computer. The order in which the computer looks for the drives for your operating system is the drive-startup sequence. If you are working with multiple operating systems, you might want to change the drive-startup sequence to load the operating system from the hard disk without first checking the diskette drive, or to do a remote program load (RPL). Attention When changing your startup sequence, you must be extremely careful when doing write operations (such as copying, saving, or formatting). Your data or programs can be overwritten if you select the wrong drive. For more information about the selectable drive-startup sequence, refer to the ThinkPad User's Guide.

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Hardware Compatibility
The computer supports most of the interfaces used by the IBM Personal Computer AT* and the Personal System/2* (PS/2*) products. In many cases, the command and status organization of these interfaces is maintained. The functional interfaces for the computer are compatible with the following: The Intel 8259 interrupt controllers (edge trigger mode). The Intel 8254 timers driven from 1.193 MHz (channels 0, 1, and 2). The Intel 8237 DMA controller-address/transfer counters, page registers, and status fields only. The command and request registers, and the rotate and mask functions, are not supported. The mode register is partially supported. The NS16550 serial communications controller. The Intel Pentium microprocessor. The Intel 8086**, 8088**, 80286**, 80386**, and i486DX microprocessors. The Intel 8087**, 80287**, and 80387** math coprocessors. The Intel 82077AA** diskette drive controller. The keyboard interface at addresses hex 0060 and hex 0064. Display modes supported by the IBM Monochrome Display and Printer Adapter, the IBM Color/Graphics Monitor Adapter, and the IBM Enhanced Graphics Adapter. The parallel printer ports (Parallel 1, Parallel 2, and Parallel 3) in compatibility mode.

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Error Codes
POST returns a three or more character code message to indicate which test failed. Figure 2-34 lists the failure indicated with the associated error code.

Error Code 101 102 103 104 105 107 108 109 110 111 118 127 158 159 161 162 163 173 174 175 177 178 179 183 184 185 186 188 190 191 192 195 196 201 202 203 215 221 225 301

Description Interrupt failure. Timer failure. Timer interrupt failure. Protected mode failure. Last 8042 command not accepted. NMI test failure. Timer bus test failure. Low meg-chip select test. Planar parity. I/O parity. Planar parity error logged. Cache error. A supervisor password is set, but no hard disk password is set. The hard disk password is not identical to the supervisor password. Dead battery. Check sum or configuration error. Date and time are not set; clock not updated. CMOS CRC error. Configuration error. Bad EEPROM CRC 1. Bad supervisor password checksum. EEPROM is not functional. NVRAM error log full. Supervisor password is needed. Bad power-on password checksum. Corrupted startup boot sequence. Inconsistency between EEPROM and security lock latch 2. Bad EEPROM CRC 2. Critically low battery condition detected. PM general error. Fan error. Configuration mismatch error found during hibernation wake-up. Critical error found during hibernation wake-up. Memory data error. Memory line error 00 through 15. Memory line error 16 through 23. Memory test failure on on-board memory. ROM to RAM remap error. Unsupported memory module is installed. Keyboard error.

Figure 2-34 (Part 1 of 2). Error Codes

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Error Code 601 602 604 1101 1201 1701 1780, 1790 1781, 1791 2401 8081 8082 8601 8602 8603 8611 8612 8613 I9990301 I9990302 I9990303 I9990305

Description Diskette drive or controller error. No valid boot record on diskette. Invalid diskette drive error. Serial-A test failure. Serial-B test failure. Hard disk controller failure. Hard disk 0 error. Hard disk 1 error. System board video error. PCMCIA presence test failure (PCMCIA revision number also checked). PCMCIA register test failure. System bus error (8042 mouse interface). External mouse error. System bus error or mouse error. System bus error (I/F between 8042 and IPDC). TrackPoint error. System board or TrackPoint error. Hard disk error. Invalid hard disk boot record. Bank-2 flash ROM checksum error. No bootable device.

Figure 2-34 (Part 2 of 2). Error Codes

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Section 3. Subsystems
Video Subsystem . . . . . . . . . . Video Modes . . . . . . . . . . . Modem Subsystem . . . . . . . . . ThinkPad Modem . . . . . . . . MIDI Port Function . . . . . . . Sound Blaster Support Function Telephony (Modem) Function . Audio Subsystem . . . . . . . . . . MIDI Port Function . . . . . . . Sound Blaster Support Function Audio Port Specifications . . . . Infrared (IR) Subsystem . . . . . . IRQ Level and DMA Channel . PC Card Subsystem . . . . . . . . Pin Assignments . . . . . . . . . IDE Channel on the UltraSlim Bay MIDI/Joystick Port . . . . . . . . . MIDI Interface . . . . . . . . . . Joystick Interface . . . . . . . .
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