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5 4 3 2 1
JE70-CP Block Diagram Project code: 91.4HN01.001
PCB P/N : 48.4HN01.0SD
SYSTEM DC/DC
RT8223
INPUTS OUTPUTS
REVISION : 09923_-1M 5V_S5
DDRIII Slot 0 DDRII Channel A DCBATOUT
Clock Generator 800/1066/1333 20 3D3V_S5
Intel CPU RGB CRT
CRT 24 47
ICS9LRS3197AKLFT
D
3
DDRIII Slot 1
Arrandale Madison SYSTEM DC/DC D
DDR II Channel B RT8209E
800/1066/1333 21
Clarksfield PCI EXPRESS GRAPHIC LVDS 1CH
LCD
23
INPUTS OUTPUTS
4,5,..,9,10 WXGA+
X16 ATI
DDRIII Slot 2 DDR II Channel B DCBATOUT 1D5V_S3
800/1066/1333 22 Digital Display 48
22 HDMI 25
FDIx8 DMIx4 SYSTEM DC/DC
RT8209B
INPUTS OUTPUTS
WEBCAM 23
Mini-Card INTEL DCBATOUT 1D05V_S0
PCIE+USB 2.0 49
WLAN 37
BLUETOOTH
28
PCH SYSTEM DC/DC
TPS51611
14 USB 2.0/1.1 ports USB 2.0 USB x1 INPUTS OUTPUTS
29
Giga LAN ETHERNET (10/100/1000Mb)
C RJ45 PCIE C
CONN BCM57780 High Definition Audio DCBATOUT GFX_CORE
31 52
30 6 SATA ports
8 PCIE ports CPU DC/DC
ACPI 1.1
USB x 2 TPS51621
INPUTS OUTPUTS
LPC I/F
MIC IN HD AUDIO PCI/PCI BRIDGE DCBATOUT VCC_CORE
CODEC AZALIA Card Reader 45,46
SD/MMC
INT MIC ALC272 32 AU6437
MS/MS Pro/xD
MAXIM CHARGER
BQ24745
LINE OUT
INPUTS OUTPUTS
SATA SATA HDD 26
DCBATOUT BT+
B B
51
OP AMP
G1454 SPI
33
SATA ODD 27 PCB STACKUP
11,12,...,18,19
TOP
GND
LPC Bus LPC debug 40 Flash ROM S
4MB 40
S
2CH SPEAKER KBC GND
SPI
ENE3930 BOTTOM
39
A Pre UMA A
Thermal Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Flash ROM Touch Int. Taipei Hsien 221, Taiwan, R.O.C.
Sensor 38
128KB 40 PAD41
KB39 Title
G792
Block Diagram
CPU FAN Size Document Number Rev
A3
JE70-CP -1M
Date: Tuesday, February 02, 2010 Sheet 1 of 67
5 4 3 2 1
A B C D E
PCH Strapping Processor Strapping
Name Schematics Notes Pin Name Strap Description Configuration (Default value for each bit is Default
SPKR Reboot option at power-up 1 unless specified otherwise) Value
Default Mode: Internal weak Pull-down.
CFG[4] Embedded 1: Disabled - No Physical Display Port attached to 1
No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-k Embedded DisplayPort.
- 10-k weak pull-up resistor. DisplayPort
Presence 0: Enabled - An external Display Port device is
INIT3_3V# Weak internal pull-down. Do not pull high. connected to the Embedded Display Port.
4 GNT3#/ Default Mode: Internal pull-up. CFG[3] PCI-Express Static 1: Normal Operation. 1
4
GPIO55 Low (0) = Top Block Swap Mode (Connect to ground with 4.7-k weak Lane Reversal 0: Lane Numbers Reversed 15 -> 0, 14 -> 1, ...
pull-down resistor).
CFG[0] PCI-Express 1: Single PCI-Express Graphics 1
INTVRMEN High (1) = Integrated VRM is enabled Configuration 0: Bifurcation enabled
Low (0) = Integrated VRM is disabled Select
GNT0#, Default (SPI): Left both GNT0# and GNT1# floating. No pull up
GNT1# required. CFG[7] Reserved - Clarksfield (only for early samples pre-ES1) - 0
Temporarily used Connect to GND with 3.01K Ohm/5% resistor
Boot from PCI: Connect GNT1# to ground with 1-k pull-down
resistor. Leave GNT0# Floating. for early Note: Only temporary for early CFD samples
Clarksfield (rPGA/BGA) [For details please refer to the WW33
Boot from LPC: Connect both GNT0# and GNT1# to ground with 1-k samples. MoW and sighting report].
pull-down resistor. For a common motherboard design (for AUB and CFD),
GNT2#/ Default - Internal pull-up. the pull-down resistor should be used. Does not
GPIO53 Low (0)= Configures DMI for ESI compatible operation (for servers impact AUB functionality.
only. Not for mobile/desktops).
GPIO33 Default: Do not pull low.
Disable ME in Manufacturing Mode: Connect to ground with 1-k
pull-down resistor.
SPI_MOSI Enable iTPM: Connect to Vcc3_3 with 8.2-k weak pull-up resistor.
3 Disable iTPM: Left floating, no pull-down required. 3
NV_ALE Enable Danbury: Connect to Vcc3_3 with 8.2-k weak pull-up
resistor.
Disable Danbury: Connect to ground with 4.7-k weak pull-down
resistor.
NC_CLE Weak internal pull-up. Do not pull low.
HAD_DOCK_EN# Low (0): Flash Descriptor Security will be overridden.
/GPIO[33] High (1) : Flash Descriptor Security will be in effect.
HDA_SDO Weak internal pull-down. Do not pull high.
HDA_SYNC Weak internal pull-down. Do not pull high.
GPIO15 Weak internal pull-down. Do not pull high.
GPIO8 Weak internal pull-up. Do not pull low.
GPIO27 Default = Do not connect (floating)
High(1) = Enables the internal VccVRM to have a clean supply for
analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board filter
circuits for analog rails.
2 2
USB Table
PCIE Routing
Pair Device
LANE1 LAN 0 USB3
LANE2 MiniCard1 1 USB2
2 USB4
LANE3 MiniCard2 3 MINICARD1
4 WECAM
5 Touch Panel
6 NC
7 NC
8 NC
9 USB1(HS)
10 Finger Print Pre UMA
1 11 Blue Tooth 1
12 MINIC2 Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
13 Cardreader Taipei Hsien 221, Taiwan, R.O.C.
Title
Table of Content
Size Document Number Rev
A3
JE70-CP -1M
Date: Tuesday, February 02, 2010 Sheet 2 of 67
A B C D E
1D5V_S0_CLKGEN
-1M 0127 1D5V_S0_CLKGEN
1
1
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C736 C345
1D5V_S0 R6261 2
0R3J-0-U-GP 1D05V_S0
2
2
1 R242 2
R269 0R0603-PAD
1 2 1D5V_S0_CLKGEN
3D3V_S0 Do Not Stuff 3D3V_S0
DY
4 4
1 R273 2 3D3V_CK505 3D3V_CK505_IO R243 1 2
0R0603-PAD C746 C339 Do Not Stuff
1
1
1
1
1
1
1
1
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
Do Not Stuff
Do Not Stuff
C745 C737 C338 C340
DY
Do Not Stuff
Do Not Stuff
C744 C341
SC1U10V2ZY-GP
SC1U10V2ZY-GP
2
2
2
2
2
2
2
2
DY DY DY
DY
VGA_XIN1_L 1 2
DY EC56 Do Not Stuff
24
17
29
15
18
1
5
U65
VDDCPU_3_3
VDDSRC_3_3
VDDREF_3_3
VDDDOT96MHZ_3_3
VDDSRC_IO
VDDCPU_IO
VDD_27MHZ
SB 1118
RN
R633
12 DREFCLK# 4 1 DREFCLK#_R 4 6 VGA_XIN1_L 1 2 JTAG_TCK 59
DOT96C_LPR 27MHZ_NONSS
RN
12 DREFCLK 0R4P2R-PAD
3 2 DREFCLK_R 3 7 OSC_SPREAD_L 1 Do Not Stuff
RN82 DOT96T_LPR 27MHZ_SS TP117 ATI_ES
4 1 CLKIN_DMI#_R 14 3D3V_S0
12 CLKIN_DMI# SRCC1_LPR
RN
12 CLKIN_DMI 0R4P2R-PAD
3 2 CLKIN_DMI_R 13 16 CPU_STOP# R241 1 2 10KR2J-3-GP
RN78 SRCT1_LPR CPU_STOP# CLK_EN
CLKPWRGD/PD#_3_3 25
12 CLK_PCIE_SATA# 4 1 CLK_PCIE_SATA#_R 11 30 FSC R258
1 2 33R2J-2-GP CLK_ICH14 12
0R4P2R-PAD CLK_PCIE_SATA_R SATAC_LPR REF_3L/FSLC_3_3
12 CLK_PCIE_SATA 3 2 10 SATAT_LPR
3 RN80 3
1
12 CLK_CPU_BCLK# 0R4P2R-PAD 3 RN77 2 CLK_CPU_BCLK#_R 22 28 GEN_XTAL_IN DY C344
CLK_CPU_BCLK_R CPUC0_LPR X1 GEN_XTAL_OUT
12 CLK_CPU_BCLK 4 1 23 CPUT0_LPR X2 27
Do Not Stuff
2
19 31
GNDDOT96MHZ
CPUC1_LPR SDATA_3_3 PCH_SMBDATA 12,20,21,22
RN
20 CPUT1_LPR SCLK_3_3 32 PCH_SMBCLK 12,20,21,22
GND27MHZ
GNDSATA
GNDCPU
GNDSRC
GNDREF
GND
-1M 0127 ICS9LRS3197AKLFT-GP-U
33
26
21
12
2
8
9
71.93197.003 DY
PCH_SMBDATA 1 2
2ND = 71.93197.B03 ECT7 Do Not Stuff