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(c) Intel Corporation, 1979
Application of Intel's Contents
5V EPROM and
INTRODUCTION ............................. 1
ROM Family for
PINOUT EVOLUTION ........................ 1
Microprocessor SYSTEM ARCHITECTURE ........... . . . . . . . .. 1
Systems BUS CONTENTION ........................... 2

INTERFACE .................................. 3

TERMINOLOGY .............................. 3

THE NEW INTEL FAMIL Y .................... 4


Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied.
This Application Note discusses how the new Intel family for the 32K devices must be derived from the 2716 in order
of 5 volt EPROMs and ROMs can be used with micro- to maintain socket compatibility. This 16K to 32K pinout
processor systems. The pinout evolution and philosophy evolution is shown in Figure 1.
are explored in detail, which leads directly to system archi-
tecture. Particular emphasis will be placed on the pitfalls
of bus contention and the microprocessor/memory inter-
face. Finally, an actual printed circuit board layout is

As EPROM/ROM technology has evolved, there are
often periods of confusion over EPROM and ROM pin-
outs, as ROM density usually leads EPROM density by a
factor of two, but ultimately users want any given EPROM
to have a ROM compatible part. As we have seen, after the
2716 16K EPROM was introduced, a new ROM pinout
emerged and "triumphed" over an earlier "standard."
The reason this ROM pinout change occurred is that as
codes stabilize in user's systems and equipment, many
users opt for the less expensive ROMs, which are mask Figure 1. 16K EPROM Determines
programmable devices. At the same time, users often use 32K ROM Pinout
the highest available density ROM so they combine
modular firmware and minimize device count. Of course,
many users never do go to the ROM stage with their equip- SYSTEM ARCHITECTURE
ment, preferring to minimize inventory levels and utilize
standard designs that can be customized for final equip- As higher performance microprocessors have become
ment configurations, but they always want the capability available, the architecture of microprocessor systems has
to do so if desired. been evolving, again placing demands on memory. For
many years, system designers have been plagued with the
In addition, over the past few years, the development of
problem of bus contention when connecting multiple
microprocessors has been intimately entwined with both
memories to a common data bus. There have been various
schemes for avoiding the problem, but device manufac-
The 1702A and its ROM counterpart, the 1302, were com- turers have been unable to design internal circuits that
pletely adequate to support the requirements of the 4004 would guarantee that one memory device would be "off"
series of microprocessors. In order to support the 5 volt, the bus before another device was selected. With small
3MHz 8085A and 5MHz 8086, it is desirable to use a com- memories (512x8 and 1Kx8), it has been traditional to con-
patible device such as the Intel 5 volt 2716, whose 450ns ac- nect all the system address lines together and utilize the dif-
cess time is compatible with the microprocessor re- ference between tACC and tco to perform a decode to
quirements. Some high performance versions of these pro- select the correct device (as shown in Figure 2).
cessors may require selected versions of the 2716 (such as
the 2716-1 with tACC = 350ns, or the 2716-2 with
tACC = 390ns) depending on the actual system configura-
tion. ,----------,

Summarizing these events since the introduction of the In-
tel 1702A, which was the first EPROM, we can postulate
the following hypothesis: at any point in time, the present
EPROM determines the pinout for the next generation
ROM. And, if the subsequent larger density EPROM is
not ROM compatible, the ROM will change. Also, it can
be seen that ROMs and EPROMs must evolve along with
microprocessor developments-so memory performance
does not limit system performance.
The devices which are discussed in this Application Note
represent an extension of the 5 volt compatible family to
Figure 2. Single Control Line Architecture
32K bit and 64K bit densities, while improving perfor-
mance as discussed above. It also follows that the pinout
With the l702A, the chip select to output delay was only
lOOns shorter than the address access time; or to state it
another way, the tAee time was 1000ns while the teo time I tACC

was 900ns. The l702A tAee performance of 1000ns was ADDRESS

suitable for the 4004 series microprocessors, but the 8080
processor required that the corresponding numbers be
, 1\
reduced to tAee = 450ns and teo = l20ns. This allowed a
substantial improvement in performance over the 4004 DATA OUT HIIIIIIIII
series of microprocessors, but placed a substantial burden DECODE
on the memory. The 2708 was developed to be compatible
with the 8080 both in access time and power supply re- Figure 3. Single Line Control Architecture
quirements. A portion of each 8080 machine cycle time
had to be devoted to the architecture of the system
decoding scheme used. This devoted portion of the 2708 #1
machine cycle included the time required for the system Vee I Vee
controller (8224) to perform its function before the actual I
decode process could begin. I
Let's pause here and examine the actual decode scheme TIE
that was used so we can understand how the control func-
tions that a memory device requires are related to system
) I

architecture. I
The 2708 can be used to illustrate the problem of having a I
single control line. The 2708 has only one read control I
function, chip select (CS), which is very fast (teo = l20ns) I
with respect to the overall access time (tAee = 450ns) of I
Vss Vss
the 2708. It is this time difference (330ns) that is used to I
perform the decode function, as illustrated in Figure 3. L_________ _
The scheme works well and does not limit system perfor- BUS
mance, but it does lead to the possibility of bus contention. Figure 4. Results of Improper Timing when OR Tying
Multiple Memories
There are actually two problems with the scheme described
in the previous section. First, if one device in a multiple the device that is selected. The result is the same as before
memory system has a relatively long deselect time, and a - bus contention, only from a different source. The
relatively fast decoder is used, it would be possible to have deselected device cannot get "off" the bus before the
another device selected at the same time. If the two devices selected one is "on" the bus as the addresses rapidly
thus selected were reading opposite data; that is, device change state. One approach to solving this problem would
number one reading a HIGH and device number two be to design (and specify as a maximum) devices with tDP
reading a LOW, the output transistors of the two memory time less than teo time, thereby assuring that if one device
devices would effectively produce a short circuit, as Figure is selected while another is simultaneously being
4 illustrates. In this case, the current path is from Vee on deselected, there would be some small (20ns) margin. Even
device number one to GND on device number two. This with this solution, the user would not be protected from
current is limited only by the "on" impedance of the MOS devices which have very fast teo times (teo is specified as a
output transistors and can reach levels in excess of 200mA maximum).
per device. If the MOS transistors have a lot of "extra" The only sure solution appears to be the use of an external
margin, the current is usually not destructive; however, an bus driver Itransceiver that has an independent enable
instantaneous load of 400mA can produce "glitches" on function. Then that function, not the "device selecting
the Vee supply - glitches large enough to cause standard function," or addresses, could control the flow of data
TTL devices to drop bits or otherwise malfunction, thus "on" and "off" the bus, and any contention problems
causing incorrect address decode or generation. would be confined to a particular card or area of a large
The second problem with a single control line scheme is card. In fact, many systems are implemented that way -
more subtle. As previously mentioned, there is only one the use of bus drivers is not at all uncommon in large
control function available on the 2708 and any decoding systems where the drive requirements of long, highly
scheme must use it out of necessity. In addition, any in- capacitive interconnecting lines must be taken into con-
advertent changes in the state of the high order address sideration - it also may be the reason why more system
lines that are inputs to the decoder will cause a change in designers were not aware of the bus contention problem
until they took a previously large (multicard) system and,
using an advanced microprocessor and higher density
memory devices, combined them all on one card, thereby
eliminating the requirement for the bus drivers, but ex- SELECTION

periencing the problem of bus contention as described
\ I
above. \ I

THE MICROPROCESSOR/MEMORY Figure 5. Two Control Line Architecture

From the foregoing discussion, it becomes clear that some
new concepts, both with regard to architecture and perfor- ADDRESS
mance are required. A new generation of two control line ~--~

EPROM devices is called for with general requirements as
listed below:

1. Complete ROM pin and function compatibility.
2. A power control function that allows the device to
enter a low-power standby mode when deselected. This
function can be used as the primary device selecting func-
tion, independent of the output control. DECODE
~----_------------_-. _J


3. Capability to control the data "on" and "off" the
system bus, independent of the device selecting function
identified above.
4. Access time compatible with the high performance Figure 6. Two Control Line Architecture
microprocessors that are currently available.

Now let's examine the system architecture that is required
to implement the two line control and prevent bus conten-
tion. This is shown in the form of a timing diagram (Figure TERMINOLOGY
5). As before, addresses are used to generate the unique
device selecting function, but a separate and independent Some of the terminology applied to the functions of the
Output Enable (OE) control is now used to gate data "on" Intel 5 volt compatible family may be confusing or un-
and "off" the system data bus. With this scheme, bus con- familiar to many EPROM/ROM users, so the various
terms are defined here. Actually, the nomenclature was
tention is completely eliminated as the processor deter-
developed by various standards groups and is reiterated
mines the time during which data must be present on the
bus and then releases the bus by way of the Output Enable here to avoid confusion as we begin a detailed discussion
line, thus freeing the bus for use by other devices, either of the devices themselves.
memories or peripheral devices. This type of architecture
First of all, Chip Enable (CE) must be defined, as it is the
can be easily accomplished if the memory devices have two
primary device selection pin. By agreed standards, that
control functions, and the system is implemented accor-
function which substantially affects power dissipation is
ding to the block diagram shown in Figure 6. It differs
called CEo Any memory device that has a CE function has
from the previous block diagram (shown in Figure 2) in
both an active and standby power level associated with it.
that the control bus, which is connected to all memory
Output Enable pins, provides separate and independent Output Enable (OE) is the signal that controls the output.
control over the data bus. In this way, the microprocessor The fundamental purpose of OE is to provide a completely
is always in control of the system; while in the previous separate means of controlling the output buffer of the
system, the microprocessor passed control to the particular memory device, thereby eliminating bus contention.
memory device and then waited for data to become
available. Another way to look at it is, with a single control Chip Select (CS) is a signal that gets logically ANDed with
line the system is always asynchronous with respect to addresses. In a completely static device, CS must remain
microprocessor/memory communications. By using two stable throughout the entire device cycle, and its function
control lines, the memory is synchronized to the processor. is equivalent to Output Enable (OE).
THE NEW INTEL FAMILY The highest density member of the family is a 64K ROM
Figure 7 shows the new Intel 5 volt compatible family of which is also shown in Figure 7. In order to maintain total
EPROMs and ROMs. In order to take advantage of the compatibility it is packaged in a standard 28-pin package.
modular compatibility offered by the family, the func- It may seem as though the 28 pin package is not compatible
tional compatibility of device pins 18, 19 and 21 must be with the rest of the family, but referring again to Figure 7,
understood. (Shaded area in Figure 7.) note that the lower 24 pins are identical to the 24 pin 8K,
First, we must examine the compatibility of the two oldest 16K and 32K devices. To allow for total compatibility
EPROM members of the 5 volt family - the 8K (2758) and within the family: printed circuit boards must be laid out
the 16K (2716). to accommodate 28 pin sites; a jumper must be included to
accommodate pin 21 as shown in Figure 8, and when using
Pin 21 (V pp) is normally connected to Vcc for read only 64K devices, CS2 (Pin 26) must be mask coded active high.
applications of both devices, and pin 19 is either at GND This compatibility can also be seen graphically in Figures 9
(VId for the 8K 2758 or connected to AlO for the 16K
and 10. The upper portion of the figure shows how 24 pin
2716. Further details on either of these devices can be
devices are used in the 28 pin sites. The two control lines
found in Section 9 of the 1977 Edition of the Intel Memory
(CE and OE) remain unchanged as discussed earlier, and A12,
Design Handbook, or Section 4 of the 1978 Intel Data
the next address bit required for a 64K bit device, is
Catalog. connected to pin 2 of the 28 pin site. The lower portion of
The 32K (4Kx8) devices, which have identical pinouts for the figure illustrates the use of 28 pin devices. Address bit
both the ROM and EPROM, will now be discussed. Pin 18 Al2 is already connected to the right pin, and the chip
is CEo Pin 19 is AlO, while pin 20 is DE. As was pointed out selects (CS} and CS2) are connected to the Vcc power
before, Output Enable is the function which allows in- distribution grid. This configuration would require that
dependent control of the data "on" and "off" the output both CSt and CS2 be coded active high.
bus. As Figure 7 indicates, V pp (the programming voltage
for the 2732 EPROM) is now multiplexed with OE on pin Vee

20. Pin 21 becomes All, which is the additional address bit A11~""--'
that is required as the density increases from 16K to 32K.
Pin 21 is the only pin that requires any special considera-
tion when designing a system to accept the 8K, the 16K, or
the 32K device. With the 8K and the 16K devices, pin 21
must be connected to Vcc, while with the 32K and higher
density devices, it must be connected to All. This is easily
accomplished by making sure the printed circuit trace links 32K Bit Density and Higher
all pin 21 's together as though they were an address line
and allowing for a jumper that will connect pin 21 to either
Vcc or All at the edge of the array (this technique can be A11 -----<;;
seen in the "Printed Circuit Board Design" section and in
Figure 8). Connecting the pin 21 's together in this manner
is acceptable as the read current requirement for V pp is
4mA maximum per device - low enough to be handled by
a signal trace, but too high for an address driver to provide
8K and 16K Density Devices

Figure 8. Pin 21 Connections for Various Density Devices

271S 2732 A12
A7 A7
A5 A5 A5
A4 A4 A4
A3 A3 A3
A2 A2 A2
A1 A1 A1
00 00 00
01 01 01
02 02 02


Figure 7. 5 Volt EPROM/ROM Compatible Family




III 24PIN at III 24 PIN at ID 24 PIN at
ID 8, 16 III III 8,16 at III 8, 16 at
OR 32K OR 32K OR 32K
ID at III at ID at
III at III at III at

.. .. ..
III at ID at ID at
III at III at III at

24 Pin Devices and 28 Pin Sites





.. ..
ID at III at III at

ID 28 PIN at III 28 PIN
at III 28PIN


III 64K at 64K III 64K


.. ..
ID at III at III at


.. .. ..
III at III at ID at
ID III at III at
28 Pin Devices and 28 Pin Sites Figure 9.

In some systems, additional logic may be used to imple- decoupling is to overcome the voltage droop caused by the
ment a "special" decode of CSl to allow for ROM to inductive effects of the PC board traces. Electrolytic or
ov~rlap RAM when a system bootstrap program is being tantalum capacitors are suitable for bulk decoupling. The
loaded; that additional logic should be implemented with following capacitance values and locations are
CSl; CS2 should be coded active high in order to preserve recommended for the 16K and 32K:
total compatibility.
1. A 0.1 J-lF ceramic capacitor between Vee and GNO at
To summarize, the selection of a 28 pin package for 64K every other device.
devices has several benefits of importance to present and 2. A 4.7 J-lF electrolytic capacitor between Vee and G NO
future system designs:
for each eight devices.
1. Two line control philosophy (separate CE and OE A printed circuit board layout for a total array of 16
functions) is preserved at the 64K bit level. devices is shown in Figure 10. This printed circuit layout
2. 64K EPROM compatibility is allowed for by maintain- incorporates a power supply distribution system such that
ing a pin for the Vpp function.
the power supply and ground traces on the PC board are
3. The next generation (128K bit ROM) must be in a 28
gridded both vertically and horizontally at each memory
pin package.
device; this technique minimizes the power distribution
If CS2 (pin 26) is mask coded to be active high and con- system impedance and enhances the effect of the
nected to Vcc, and the jumper provision for pin 21 is in- decoupling capacitors. Provisions are included for all
cluded on the card as described above, any member of the address inputs, output enable inputs, data outputs and
family can be plugged into the same socket - 1K, 2K, 4K decoded chip enable inputs. The 0.1 J-lF capacitors referred
or 8K bytes - without any card modification or redesign. to above are included for every other device (indicated by
In addition, future devices of higher density will fit in the the legend C2) while the bulk decoupling capacitor is
same pinout. shown at the upper left-hand corner (indicated by the
legend C1). The layout consists of four rows of four 28-pin
device sites each and embodies all of the concepts
PRINTED CIRCUIT BOARD DESIGN explained above. Note that pins 28, 27 and 26 are all
The 2716 and the 2732 are both completely static devices connected to Vee. This requires that when ordering mask
that automatically enter a low power standby mode programmed 64K ROMs, the order must specify that CS I
whenever CE is high. When CE is taken low, the device and CS2 be coded active HIGH. The single jumper
"powers up" and enters the active mode. This change provision discussed in the previous section is also included
from standby to active power can cause transient currents at the upper lefthand corner of the array (indicated by A,
that must be suppressed by properly selected decoupling B, and C). Pad B is connected to pin 21 of all devices in the
capacitors. High quality, high frequency ceramic array; pad A should be conn.ected to the All address driver
capacitors of small physical size with low inherent and pad C is connected to Vee. For use with 32K bit or
inductance should be used. In addition, bulk decoupling larger devices, a jumper must be installed between pads A
must be provided, usually near where the power supply is and B; for use with the 2716 (16K) or the 2758 (8K), the
connected to the array. The purpose of the bulk jumper must be installed between pads Band C.