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5 4 3 2 1
31ZY8MB0000
ZY8 MB ASSY(DC/GM/MXM)ASSY W/O CPU
31ZY8MB0010
ZY8 SYSTEM BLOCK DIAGRAM DDR PWR
TPS5116 P35
CHARGER
ISL6251 P31
ZY8 MB ASSY(QC/GM/MXM)ASSY W/O CPU
X'TAL
THERMAL 3/5V SYS PWR
14.318MHz PROTECTION P38 ISL6237 P32
Penryn 479 Thermal Sensor Fan Driver
D
CLOCK GENERATOR uFCPGA (NS LM95245) (PWM Type) 2.5V/ 1.5V PWR CPU CORE PWR D
P3, P4 P3 P29 DISCHARGER P37 ISL6262A P33
SELGO: SLG8SP513VTR
DC/QC support
P2 POWER TREE +1.05V
P? RT8202 P34
FSB
667/800/1067 Mhz
HDMI Level Shift
P19
DISPLAY PORT
HDMI DISPLAY PORT
P19
DDR III NB PCIE MXM 3.0 CRT
SO-DIMM 0 Dual Channel DDR3 Cantiga LVDS
CRT HDMI
SO-DIMM 1 800/ 1066 MHz P17 P19
P16 GM45 LVDS
C
P5, P6, P7, P8, P9, P10, P11 LVDS & CRT CRT P18 C
Switch
P18 LVDS P18
HDD (SATA) *2
P22 X4 DMI interface USB1
SATA0
PCI-Express PCIE-2 New Card
eSATA Conn. eSATA Buffer SATA4
(TI SN75LVCP412) P28 ODD (SATA) SB USB1 P25
USB0 P28 SATA1
P22 ICH9M
PCIE-4&6 Mini Card
SATA5
USB Port x 4 WLAN / TV
USB2, 3, 5 P28
USB 2.0 USB4 & 6 P21
B PCIE-5 and USB9 are free. X'TAL PCIE-1 PCIE-3 B
32.768KHz X'TAL
Bluetooth Azalia P12,P13,P14,P15
25MHz
USB8 P29
USB4 & 6
IEEE1394 & Broadcom
CCD LPC Giga-LAN
USB11 P29 X'TAL
Media Cardreader
32.768KHz (OZ888GS0LN) (BCM5764/ BCM5784)
P26 P20
FingerPrint Audio CODEC EC (WPC775C)
USB9 P29 (ALC889X) P23
P30
IEEE1394a Card Reader Transformer P20
connector Connector
P26 P26
SPI ROM
P30
RJ45 P20
A A
Front Stereo Amp Center Mono Amp Rear Audio Amp Sub-Amplifier
(G1453L/ 2W+2W) (G1442/ 2W) & Head phone (MAX9737) Touch Pad MMB SSID: 019F and 019E
P24 P23 AN12947A P23,P24 P24 P29 P27 SVID: 1025
Quanta Computer Inc.
Front Speaker Center Speaker Speaker S/PDIF SUBWOOFER Line in MIC Jack Int. D-MIC PROJECT : ZY8
K/B COON. CIR Size Document Number Rev
P24 P24 P24 P24 P24 P24 P24 P18, P24 P29 P30
2A
ZY8 Block Diagram
Date: Tuesday, December 30, 2008 Sheet 1 of 39
5 4 3 2 1
5 4 3 2 1
Clock Generator L48
FB 180ohm/1.5A
BKP1608HS181-T
250mA(Max.)
+3V_CLK
U15
+3V 4 VDD_REF NC 55
9 VDD_PCI
C116 C84 C119 C78 C111 C92 C87 16 7 CGCLK_SMB
VDD_48 SCLK CGDAT_SMB
23 VDD_PLL3 SDA 6
10u_6 .1u_4 *.1u_4 .1u_4 *.1u_4 .1u_4 .1u_4 46 CK505
VDD_SRC
62 VDD_CPU SRC5/PCI_STOP# 45 PM_STPPCI# [14]
SRC5#/CPU_STOP# 44 PM_STPCPU# [14]
CLK VDD power range 1.05V~3.3V
80mA(Max.) 61
D CPU0 CLK_CPU_BCLK [3] D
+1.05V L18 BKP1608HS181-T +1V05_CLK 19 60
VDD_IO CPU0# CLK_CPU_BCLK# [3]
FB 180ohm/1.5A 27
C97 C77 C76 C86 C109 C118 C120 VDD_PLL3_IO
33 VDD_SRC_IO_1 CPU1 58 CLK_MCH_BCLK [5]
43 VDD_SRC_IO_2 CPU1# 57 CLK_MCH_BCLK# [5]
10u_6 .1u_4 .1u_4 .1u_4 *.1u_4 .1u_4 .1u_4 52 VDD_SRC_IO_3
56 VDD_CPU_IO SRC8/ITP 54 CLK_PCIE_CARD [26]
SRC8#/ITP# 53 CLK_PCIE_CARD# [26]
At 11/21
[14] SATACLKREQ# R74 475/F_4 SATACLKREQ#_R 8 41 SWAP
PCI0/CR#_A SRC10 CLK_MXM [17]
SRC10# 42 CLK_MXM# [17]
[25] NEW_CLKREQ# R80 475/F_4 NEW_CLKREQ#_R 10
PCI1/CR#_B
SRC11/CR#_H 40 CLK_PCIE_LAN [20]
R79 33_4 PCLK_DEBUG_R 11 39
[21] PCLK_DEBUG PCI2 SRC11#/CR#_G CLK_PCIE_LAN# [20]
C95 *10p_4
R81 33_4 PCLK_591_R 12 37
[30] PCLK_591 PCI3 SRC9 CLK_PCIE_TV [21]
C98 *10p_4 38
SRC9# CLK_PCIE_TV# [21]
PCLK_PCM_R 13
R84 33_4 PCI4/SEL_LCDCLK#
[13] PCLK_ICH SRC7/CR#_F 51 CLK_PCIE_MINI1 [21]
C115 *10p_4 PCLK_ICH_R 14 50
PCIF5/ITP_EN SRC7#/CR#_E CLK_PCIE_MINI1# [21]
CPU_BSEL0 R96 2.2K_4
R101 33_4 FSA 17 48
[14] CLKUSB_48 USB_48/FSA SRC6 CLK_PCIE_ICH [13]
C121 18p_4 47
SRC6# CLK_PCIE_ICH# [13]
CPU_BSEL2 R75 10K_4 CPU_BSEL1 64 SRC4 & SRC7 SWAP at C-test
R72 33_4 FSB/TEST/MODE
C [14] 14M_ICH SRC4 34 CLK_PCIE_NEW_C [25] C
C88 *10p_4 FSC 5 35
REF0/FSC/TESTSEL SRC4# CLK_PCIE_NEW_C# [25]
C82 33p/50V_4 CG_XIN 3 31
XTAL_IN SRC3/CR#_C CLK_PCIE_3GPLL [6]
CG_XOUT 2 32
XTAL_OUT SRC3#/CR#_D CLK_PCIE_3GPLL# [6]
Y3 65 28
VSS_BODY SRC2/SATA CLK_PCIE_SATA [12]
14.318MHz 15 VSS_PCI SRC2#/SATA# 29 CLK_PCIE_SATA# [12]
18 VSS_48
C80 33p/50V_4 22 24
VSS_IO LCDCLK/27M CLK_DREFSSCLK [6]
26 VSS_PLL3 LCDCLK#/27M_SS 25 CLK_DREFSSCLK# [6]
59 VSS_CPU
30 VSS_SRC1 SRC0/DOT96 20 CLK_DREFCLK [6]
36 VSS_SRC2 SRC0#/DOT96# 21 CLK_DREFCLK# [6]
49 VSS_SRC3
1 VSS_REF CKPWRGD/PWRDWN# 63 CK_PWRGD [14] Pin 63 : It acts as a level sensitive
strobe to latch the FS pins and
SLG8SP513VTR
other multiplexed inputs.
CPU Clock select SMBus Strap table
B +3V Pin 8 : PCI_0 or CKREQ#_A selection B
+3V
0 = PCI_0 output
CPU_BSEL0 R100 0_4 R407 *10K_4 SATACLKREQ#_R
[3] CPU_BSEL0 MCH_BSEL0 [6] 1 = CKREQ#_A (Control SRC_0 & SRC_2)
CPU_BSEL1 R65 0_4
[3] CPU_BSEL1 MCH_BSEL1 [6]
R415 R414 Pin 10 : PCI_1 or CKREQ#_B selection
R404 *10K_4 NEW_CLKREQ#_R
2 0 = PCI_1 output
CPU_BSEL2 R73 0_4 10K_4 10K_4
[3] CPU_BSEL2 MCH_BSEL2 [6] 1 = CKREQ#_B (Control LCDCLK & SRC_4)
If XDP is not implemented, connect CPU to GMCH directly CGDAT_SMB 1 3 PDAT_SMB [14,16,21,25]
;Otherwise 1Kohm is required Q41
2N7002 PCLK_PCM_R R85 10K_4 Pin 13 : For Pin 20/21 and 24/25 selection
+3V 0 = LCDCLK & DOT96 for internal graphic (Setting)
BSEL Frequency Select Table 1 = 27M & 27M_SS &SRC_0 for external graphic
FSC FSB FSA Frequency
2
0 0 0 266Mhz CGCLK_SMB 1 3 PCLK_ICH_R R92 10K_4 Pin 14 : For Pin 53/54 (CPU_ITP or SRC_8) selection
PCLK_SMB [14,16,21,25]
0 = SRC_8 (Setting)
0 0 1 133Mhz Q42
2N7002 1 = CPU_ITP
A 0 1 1 166Mhz A
0 1 0 200Mhz
1 1 0 400Mhz Quanta Computer Inc.
1 1 1 Reserved PROJECT : ZY8
1 0 1 100Mhz Size Document Number Rev
2A
1 0 0 333Mhz
CLOCK GENERATOR
Date: Tuesday, February 17, 2009 Sheet 2 of 39
5 4 3 2 1
5 4 3 2 1
[5] H_A#[3..16]
U28A
H_A#3 J4 H1
A[3]# ADS# H_ADS# [5]
ADDR GROUP_0
ADDR GROUP_0
H_A#4 L5 E2 H_D#[0..15] U28B H_D#[32..47]
A[4]# BNR# H_BNR# [5] [5] H_D#[0..15] H_D#[32..47] [5]
BOM NOTE: H_A#5 L4 G5 H_D#0 E22 Y22 H_D#32
A[5]# BPRI# H_BPRI# [5] D[0]# D[32]#
H_A#6 K5 H_D#1 F24 AB24 H_D#33
H_A#7 A[6]# H_D#2 D[1]# D[33]# H_D#34
DC@ : For Dual Core M3 A[7]# DEFER# H5 H_DEFER# [5] E26 D[2]# D[34]# V24
DATA GRP 0
DATA GRP 0
H_A#8 N2 F21 H_D#3 G22 V26 H_D#35
4C@ : For Quad Core A[8]# DRDY# H_DRDY# [5] D[3]# D[35]#
DATA GRP 2
H_A#9 J1 E1 H_D#4 F23 V23 H_D#36
A[9]# DBSY# H_DBSY# [5] D[4]# D[36]#
H_A#10 N3 H_D#5 G25 T22 H_D#37
H_A#11 A[10]# H_D#6 D[5]# D[37]# H_D#38
P5 A[11]# BR0# F1 H_BREQ# [5] E25 D[6]# D[38]# U25
H_A#12 P2 IERR# H_D#7 E23 U23 H_D#39
A[12]# D[7]# D[39]#
CONTROL
H_A#13 L2 D20 H_IERR# R223 56_4 H_D#8 K24 Y25 H_D#40
H_A#14 A[13]# IERR# +1.05V DC: 56 ohm (CS05602JB17) H_D#9 D[8]# D[40]# H_D#41
P4 A[14]# INIT# B3 H_INIT# [12] G24 D[9]# D[41]# W22
D H_A#15 P1 QC: 49.9 ohm (CS04992FB31) H_D#10 J24 Y23 H_D#42 D
H_A#16 A[15]# H_D#11 D[10]# D[42]# H_D#43
R1 A[16]# LOCK# H4 H_LOCK# [5] J23 D[11]# D[43]# W24
M1 H_D#12 H22 W25 H_D#44
[5] H_ADSTB#0 ADSTB[0]# D[12]# D[44]#
C1 H_D#13 F26 AA23 H_D#45
[5] H_REQ#[0..4] RESET# H_CPURST# [5] D[13]# D[45]#
H_REQ#0 K3 F3 H_D#14 K22 AA24 H_D#46
REQ[0]# RS[0]# H_RS#0 [5] D[14]# D[46]#
H_REQ#1 H2 F4 H_D#15 H23 AB25 H_D#47
REQ[1]# RS[1]# H_RS#1 [5] D[15]# D[47]#
H_REQ#2 K2 G3 J26 Y26
REQ[2]# RS[2]# H_RS#2 [5] [5] H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 [5]
H_REQ#3 J3 G2 H26 AA26
REQ[3]# TRDY# H_TRDY# [5] [5] H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 [5]
H_REQ#4 L1 H25 U22
REQ[4]# [5] H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 [5]
[5] H_A#[17..35] HIT# G6 H_HIT# [5]
H_A#17 Y2 E4 H_D#[16..31] H_D#[48..63]
A[17]# HITM# H_HITM# [5] [5] H_D#[16..31] H_D#[48..63] [5]
H_A#18 U5 H_D#16 N22 AE24 H_D#48
H_A#19 A[18]# XDP_BPM#0 H_D#17 D[16]# D[48]# H_D#49
R3 A[19]# BPM[0]# AD4 K25 D[17]# D[49]# AD24
ADDR GROUP_1
H_A#20 W6 AD3 XDP_BPM#1 H_D#18 P26 AA21 H_D#50
H_A#21 A[20]# BPM[1]# XDP_BPM#2 H_D#19 D[18]# D[50]# H_D#51
U4 A[21]# BPM[2]# AD1 R23 D[19]# D[51]# AB22
H_A#22 Y5 AC4 XDP_BPM#3 H_D#20 L23 AB21 H_D#52
A[22]# BPM[3]# D[20]# D[52]#
DATA GRP 1
H_A#23 XDP_BPM#4 H_D#21 H_D#53
XDP/ITP SIGNALS
U1 A[23]# PRDY# AC2 T72 M24 D[21]# D[53]# AC26
DATA GRP 3
H_A#24 R4 AC1 XDP_BPM#5 H_D#22 L22 AD20 H