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5 4 3 2 1
SYSTEM DC/DC
JM41 Block
Project code: 91.4CQ01.001 TPS51125 36
PCB P/N : 48.4CQ01.011 INPUTS OUTPUTS
REVISION : 08266-1 5V_S5(6A)
Diagram
3D3V_S5(5A)
DCBATOUT
5V_AUX_S5
D
PCB STACKUP D
3D3V_AUX_S5
TOP L1
Thermal Sensor RT8202 37
Intel
CLK GEN. CPU SMSC S L2
ICS9LPRS365B Penryn SFF EMC2103 32 VCC/GND L3
INPUTS OUTPUTS
3
S L4 DCBATOUT 1D05V_S0(10A)
4,5,6
VCC/GND L5
HOST BUS 667/800/[email protected] RT8202 38
GND/VCC L6
DDR3 Cantiga-GS SFF LVDS LCD S L7
INPUTS OUTPUTS
19
MHz
800/1066 17,18 AGTL+ CPU I/F BOTTOM L8
DCBATOUT 1D5V_S3(11A)
DDR Memory I/F RGB CRT CRT
20 RT9026 39
C
DDR3 INTEGRATED GRAHPICS
LVDS, CRT I/F
C
800/1066 17,18
MHz PCIex16 HDMI INPUTS OUTPUTS
7,8,9,10,11,12 21
X4 DMI 5V_S5 DDR_VREF_S3
C-Link0
400MHz (1.2A)
Int MIC
CHARGER
MAX8731A 41
29 ICH9M SFF PCIe
6 PCIe ports
LAN
Giga LAN TXFM RJ45 INPUTS OUTPUTS
Line Out PCI/PCI BRIDGE
27 27
Atheros AR8131 26
Codec AZALIA ACPI 2.0 CHG_PWR
29 Realtek PCIe DCBATOUT
4 SATA 18V 6.0A
ALC269Q 28
Mini 1 Card
12 USB 2.0/1.1 ports 31
MIC In ETHERNET (10/100/1000MbE)
WLAN CPU DC/DC
ADP3207A
High Definition Audio USB 35
B 29 Mini 2 Card B
LPC I/F
31 INPUTS OUTPUTS
Serial Peripheral I/F 3G
Matrix Storage Technology(DO) VCC_CORE
DCBATOUT
Active Managemnet Technology(DO) 0~1.3V
29 64A
LPC BUS VGA
INT.SPKR 13,14,15,16 ISL6263A
1.5W 40
USB SPI BIOS LPC INPUTS OUTPUTS
SATA Mini USB KBC (2MB)
Winbond 34 DEBUG
HDD SATA Blue Tooth
24
Camera WPCE773LA0DG CONN. DCBATOUT
VCC_GFXCORE
22 (7A)
33
MEDIA
SATA USB KEY
36
A ODD SATA 4 Port 25 Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
23 Touch INT. Taipei Hsien 221, Taiwan, R.O.C.
SATA Cardreader Pad 35 KB 33 MS/MS Pro/xD Title
RTS5159 BLOCK DIAGRAM
SSD SATA 30 /MMC/SD Size Document Number Rev
Custom
22 30 JM41_UMA -1
Date: Monday, March 09, 2009 Sheet 1 of 40
5 4 3 2 1
A B C D E
ICH9M Integrated Pull-up Cantiga chipset and ICH9M I/O controller
ICH9M Functional Strap Definitions Rev.1.5 page 92 Hub strapping configuration
ICH9 EDS 642879 and Pull-down Resistors Montevina Platform Design guide 22339
page 218
0.5
Signal Usage/When Sampled Comment ICH9 EDS 642879 Rev.1.5
HDA_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 Pin Name Strap Description Configuration
PCIE Port Config1 bit1, pulled low.When TP3 not pulled low at rising edge SIGNAL Resistor Type/Value
Rising Edge of PWROK of PWROK,sets bit1 of RPC.PC(Config Registers: CL_CLK[1:0] PULL-UP 20K CFG[2:0] FSB Frequency 000 = FSB1067
offset 224h). This signal has weak internal pull-down Select 011 = FSB667
CL_DATA[1:0] PULL-UP 20K 010 = FSB800
others = Reserved
4 HDA_SYNC PCIE config1 bit0,
Rising Edge of PWROK.
This signal has a weak internal pull-down.
Sets bit0 of RPC.PC(Config Registers:Offset 224h)
CL_RST0# PULL-UP 20K
CFG[4:3] Reserved
4
DPRSLPVR/GPIO16 PULL-DOWN 20K CFG8
GNT2#/ PCIE config2 bit2, This signal has a weak internal pull-up. CFG[15:14]
GPIO53 Rising Edge of PWROK. Sets bit2 of RPC.PC2(Config Registers:Offset 0224h) ENERGY_DETECT PULL-UP 20K CFG[18:17]
GPIO20 Reserved This signal should not be pulled high. HDA_BIT_CLK PULL-DOWN 20K
CFG5 DMI x2 Select 0 = DMI x2
GNT1#/ ESI Strap (Server Only) ESI compatible mode is for server platforms only. HDA_DOCK_EN#/GPIO33 PULL-UP 20K 1 = DMI x4 (Default)
GPIO51 Rising Edge of PWROK This signal should not be pulled low for desttop CFG6 iTPM Host 0= The iTPM Host Interface is enabled(Note2)
and mobile. HDA_RST# PULL-DOWN 20K Interface 1=The iTPM Host Interface is disalbed(default)
HDA_SDIN[3:0] PULL-DOWN 20K 0 = Transport Layer Security (TLS) cipher
Top-Block Sampled low:Top-Block Swap mode(inverts A16 for CFG7 Intel Management suite with no confidentiality
GNT3#/ Swap Override. all cycles targeting FWH BIOS space). HDA_SDOUT PULL-DOWN 20K engine Crypto strap 1 = TLS cipher suite with
GPIO55 Rising Edge of PWROK. Note: Software will not be able to clear the confidentiality (default)
Top-Swap bit until the system is rebooted HDA_SYNC PULL-DOWN 20K
0 = Reverse Lanes,15->0,14->1 ect..
without GNT3# being pulled down. GLAN_DOCK# The pull-up or pull-down active when configured for native CFG9 PCIE Graphics Lane 1= Normal operation(Default):Lane
GLAN_DOCK# functionality and determined by LAN controller Numbered in order
GNT0#: Boot BIOS Destination Controllable via Boot BIOS Destination bit GNT[3:0]#/GPIO[55,53,51] PULL-UP 20K
SPI_CS1#/ Selection 0:1. (Config Registers:Offset 3410h:bit 11:10). 0 = Enable (Note 3)
GPIO58 Rising Edge of PWROK. GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC. GPIO[20] PULL-DOWN 20K CFG10 PCIE Loopback enable 1= Disabled (default)
Integrated TPM Enable, Sample low: the Integrated TPM will be disabled. GPIO[49] PULL-UP 20K 00 = Reserve
Rising Edge of CLPWROK Sample high: the MCH TPM enable strap is sampled CFG[13:12] XOR/ALL 10 = XOR mode Enabled
SPI_MOSI low and the TPM Disable bit is clear, the LDA[3:0]#/FHW[3:0]# PULL-UP 20K 01 = ALLZ mode Enabled (Note 3)
Integrated TPM will be enable. 11 = Disabled (default)
LAN_RXD[2:0] PULL-UP 20K
3 DMI Termination Voltage, The signal is required to be low for desktop LDRQ[0] PULL-UP 20K
CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default) 3
Rising Edge of PWROK. applications and required to be high for
GPIO49 mobile applications. LDRQ[1]/GPIO23 PULL-UP 20K 0 = Normal operation(Default):
CFG19 DMI Lane Reversal Lane Numbered in Order
PME# PULL-UP 20K
1 = Reverse Lanes
PCI Express Lane Signal has weak internal pull-up. Sets bit 27 PWRBTN# PULL-UP 20K DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3)
SATALED# Reversal. Rising Edge of MPC.LR(Device 28:Function 0:Offset D8) DMI x2 mode[MCH -> ICH]:(3->0,2->1)
of PWROK. SATALED# PULL-UP 15K
SPKR No Reboot. If sampled high, the system is strapped to the SPI_CS1#/GPIO58/CLGPIO6 PULL-UP 20K Digital Display Port 0 = Only Digital Display Port
Rising Edge of PWROK. "No Reboot" mode(ICH9 will disable the TCO Timer (SDVO/DP/iHDMI) or PCIE is operational (Default)
system reboot feature). The status is readable SPI_MOSI PULL-DOWN 20K CFG20 Concurrent with PCIe 1 =Digital display Port and PCIe are
via the NO REBOOT bit. operting simulataneously via the PEG port
SPI_MISO PULL-UP 20K
0 =No SDVO Card Present (Default)
TP3 XOR Chain Entrance. This signal should not be pull low unless using SPKR PULL-DOWN 20K SDVO_CTRLDATA SDVO Present
Rising Edge of PWROK. XOR Chain testing. 1 = SDVO Card Present
TACH_[3:0] PULL-UP 20K
0 = LFP Disabled (Default)
GPIO33/ Flash Descriptor Sampled low:the Flash Descriptor Security will be TP[3] PULL-UP 20K Local Flat Panel
HDA_DOCK Security Override Strap overridden. If high,the security measures will be L_DDC_DATA (LFP) Present 1= LFP Card Present; PCIE disabled
_EN# Rising Edge of PWROK in effect.This should only be enabled in manufacturing USB[11:0][P,N] PULL-DOWN 15K
environments using an external pull-up resister. NOTE:
1. All strap signals are sampled with respect to the leading edge of
the (G)MCH Power OK (PWROK) signal.
2. iTPM can be disabled by a 'Soft-Strap' option in the
2 Flash-decriptor section of the Firmware. This 'Soft-Strap' is 2
activated only after enabling iTPM via CFG6.
Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time.
1
1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reference
Size Document Number Rev
A3
JM41_UMA -1
Date: Sunday, March 01, 2009 Sheet 2 of 40
A B C D E
1D05V_S0 3D3V_S0
3D3V_S0
1 R61 2 1D05V_CLK_S0
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1 R195 2 3D3V_48MPWR_S0 0R0603-PAD C404 C401 C394 C397 C400 C412 3D3V_CLK_S0 1 R197 2
1
1
1
1
1
1
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
0R0603-PAD C407 C420 C393 C411 C417 C406 C418 0R0603-PAD
1
1
1
1
1
1
1
1
1
SC1U10V3KX-3GP
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
C405 C226
SC4D7U6D3V3KX-GP
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4 4
3D3V_CLK_S0 1D05V_CLK_S0
3D3V_48MPWR_S0
U27
16
46
62
23
19
27
43
52
33
56
4
9 VDDPCI
VDDREF
VDD48
VDDPLL3
VDD96_IO
VDDPLL3_IO
VDDSRC_IO