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5 4 3 2 1




SYSTEM DC/DC
Astrosphere Block Diagram TPS51125


INPUTS OUTPUTS
DDRII
DDRII 667/800 Channel A
AMD CPU Slot 0
DCBATOUT
+3VALW
D NPT Processor +5VALW D


Rev. G DDRII
DDRII 667/800 Channel B SYSTEM DC/DC
S1G2 package Slot 1
7,8
TPS51116
3,4,5,6

HyperTransport INPUTS OUTPUTS
16X16
6.4GB/S +1.8V
DCBATOUT
+0.9V
HDCP HDCP HDCP HDMI HDMI TVOUT SYSTEM DC/DC
EEPROM 14
APL5913
RGB CRT CRT
14
INPUTS OUTPUTS

PCI-E X 1
9,10,11,12,13
+1.8V +1.2V
Mini Card PCIE x 1 PCI-E X 1
C X5 C
802.11a/b/g27
27MHz
LCD
nVIDIA 17 MAXIM CHARGER
LVDS Dual Channel MAX8731AETI
UP to 1920 X 120116 MCP67
ACPI 2.0
RJ45 10/100 INPUTS OUTPUTS
RGMII MAC
CONN 29 REALTEK
Bluetooth BT+
RTL8201N28,29 32
DCBATOUT 18V 3.0A
X2 5V 100mA
12MHz
25 Realtek Webcam
15
USB 2.0 CPU DC/DC
SD/MMC RTS5158 ISL6265
MS/MS Pro/xD
25 25
8xUSB 2.0 USB 2.0 USBx3
24
INPUTS OUTPUTS
AMOM VCC_CORE
ODD
B RJ11 MODEM 24
DCBATOUT 1.35V
B

CONN CX20548-11Z HD AUDIO HD AUDIO 35A
SATA SATA HDD
24
LINE OUT
HD AUDIO PCB LAYER
CODEC LPC I/F LPC Bus
CX20561-14Z 17,18,19,20,21,22
L1:SIGNAL 1
33
L2:VCC
MIC IN
L3:SIGNAL 2
X4 X3 SPI
INTERNAL MIC ARRAY KBC L4:SIGNAL 3
25MHz 32.768KHz
17 17 WINBOND L5:GND
WPCE773L
30
OP AMP L6:SIGNAL 4

A
34 GMT G1431
A
34
X1 Wistron Corporation
2CH SPEAKER 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
32.768KHz Touch Int. Thermal FlashRom Taipei Hsien 221, Taiwan, R.O.C.
30
Pad KB & Fan 1MB Title
32 32 G792 23 31
Block Diagram
Size Document Number Rev
A3
Astrosphere SA
Date: Monday, June 09, 2008 Sheet 1 of 44

5 4 3 2 1
5 4 3 2 1

CPU_CORE
5V/3.3V
ISL6265
TI TPS51125
VID Setting Output Signal Input Signal Output Signal
CPU_SVD
SVD +3VS PWR_S5_EN
D CPU_SVC PWRG(OD / 3.3V) 51125_ENTIP1 3D3V_PWR D
SVC PGOOD1
51125_ENTIP2 PGOOD2
Input Signal
VCORE_EN
ENABLE
Input Power Output Power
Output Power
+5VALW (6A)
+VCC_CORE0 DCBATOUT_TPS51125 VO1
Voltage Sense +VCC_CORE(O) VIN
CPU_VDD0_RUN_FB_H
VSEN0(I / Vcore) +VCC_CORE1
CPU_VDD0_RUN_FB_L +VCC_CORE(1) +3VALW (6A)
RTN0(I / Vcore) VO2
CPU_VDD1_RUN_FB_L +VDDNB
VSEN1(I / Vcore) +VDD_NB
CPU_VDD1_RUN_FB_H
RTN1(I / Vcore)
CPU_VDDNB_RUN_FB_H
VSEN_NB(I / Vcore)
CPU_VDDNB_RUN_FB_L +1.1VS_CHIP
RTN_NB(I / Vcore)
SC412A
Input Power
C DCBATOUT
VIN Input Signal Output Signal
C
+5VS PM_SLP_S3# +3VALW
VCC EN PGOOD



Charger Input Power Output Power

MAX8731A +5VALW
VCC +1.1VS_CHIP(9A)
VO1
Input Signal Output Signal

AD_IA
FBSA INP +1.8V/ +0.9VP
BT+SENSE
FBSB TPS51116
Input Power Output Power
Input Signal Output Signal
B +3VL PM_SLP_S5# +3VALW B
VDD DCBATOUT EN PGOOD
VOUT(O)
AD+ VTTEN
DCIN


Input Power Output Power
+5VALW
+1.8V_RUN_P(12A)
VDDP VO1
+1.8V_RUN_P
VTTIN +0.9VP(1.5A)
VTT
+1.0VS SC471A
+1.5V_VS
Input Signal Output Signal APL5913
PM_SLP_S3# +3VS
EN PGOOD Input Signal Output Signal
PM_SLP_S3# POK
EN

A Input Power Output Power A
+5VALW Output Power +1.5VS(4A) Wistron Corporation
VCC +1.0VS (9A) Input Power 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
VO1 +1.8V VOUT Taipei Hsien 221, Taiwan, R.O.C.
VCC
Title
Power Diagram
Size Document Number Rev
A3
Astrosphere SA
Date: Monday, June 09, 2008 Sheet 2 of 44
5 4 3 2 1
HT
CPU VLDT MAX 1.5A
+1.2VS_HT_CPU
LAYOUT: PLACE CLOSE TO CPU
ALONG HT POWER SHAPE



C429 C227 C411 C220 CPU1A DYC260 C228 C422




1




1




1




1




1




1




1
SC180P50V2JN-1GP




SC180P50V2JN-1GP
SCD22U16V3ZY-GP




SCD22U16V3ZY-GP




SC4D7U10V5ZY-3GP




SC4D7U10V5ZY-3GP




SC4D7U10V5ZY-3GP
SKT638_S1G2
D SEC 1 OF 6 D




2




2




2




2




2




2




2
LDT
D1 V_HT_A1 V_HT_B1 AE2
D2 V_HT_A2 V_HT_B2 AE3
D3 V_HT_A3 V_HT_B3 AE4
D4 V_HT_A4 V_HT_B4 AE5
PV 0408
LDT_RST# B7 RESET* LDTREQ* C6 LDT_REQ# LDT_REQ# 9
LDT_PWROK A7 PWROK
+1.8V CPUCADOUT[15..0] 9
LDT_STP# F10 LDTSTOP*
CPUCADOUTJ[15..0] 9
HT_TXD_P15 T4 CPUCADOUT15
RN63 9 NB0CADOUT[15..0]
HT_TXD_P14 V5 CPUCADOUT14
LDT_PWROK 9 NB0CADOUTJ[15..0] NB0CADOUT15 CPUCADOUT13
3 2 N5 HT_RXD_P15 HT_TXD_P13 V4
4 1 NB0CADOUT14 M3 HT_RXD_P14 HT_TXD_P12 Y5 CPUCADOUT12
NB0CADOUT13 L5 HT_RXD_P13 HT_TXD_P11 AB5 CPUCADOUT11
NB0CADOUT12 K3 HT_RXD_P12 HT_TXD_P10 AB4 CPUCADOUT10
LDT_RST# SRN300J-3-GP NB0CADOUT11 CPUCADOUT9
H3 HT_RXD_P11 HT_TXD_P9 AD5
NB0CADOUT10 G5 HT_RXD_P10 HT_TXD_P8 AD4 CPUCADOUT8
NB0CADOUT9 F3 HT_RXD_P9 HT_TXD_P7 T1 CPUCADOUT7
NB0CADOUT8 E5 HT_RXD_P8 HT_TXD_P6 U2 CPUCADOUT6
LDT_REQ# 2 1 R116 NB0CADOUT7 N3 HT_RXD_P7 HT_TXD_P5 V1 CPUCADOUT5
300R2J-4-GP NB0CADOUT6 L1 HT_RXD_P6 HT_TXD_P4 W2 CPUCADOUT4
NB0CADOUT5 L3 HT_RXD_P5 HT_TXD_P3 AA2 CPUCADOUT3
MCP77 NB0CADOUT4 J1 HT_RXD_P4 HT_TXD_P2 AB1 CPUCADOUT2
LDT_STP# 2 1 R414 NB0CADOUT3 G1 HT_RXD_P3 HT_TXD_P1 AC2 CPUCADOUT1
300R2J-4-GP NB0CADOUT2 G3 HT_RXD_P2 HT_TXD_P0 AD1 CPUCADOUT0
NB0CADOUT1 E1 HT_RXD_P1
NB0CADOUT0 E3 HT_RXD_P0 HT_TXD_N15 T3 CPUCADOUTJ15
+1.8V
C NB0CADOUTJ15 P5 HT_RXD_N15
HT_TXD_N14
HT_TXD_N13
U5
V3
CPUCADOUTJ14
CPUCADOUTJ13 C
NB0CADOUTJ14 M4 HT_RXD_N14 HT_TXD_N12 W5 CPUCADOUTJ12
NB0CADOUTJ13 M5 HT_RXD_N13 HT_TXD_N11 AA5 CPUCADOUTJ11
NB0CADOUTJ12 K4 HT_RXD_N12 HT_TXD_N10 AB3 CPUCADOUTJ10
U11A NB0CADOUTJ11 CPUCADOUTJ9
14




H4 HT_RXD_N11 HT_TXD_N9 AC5
NB0CADOUTJ10 H5 HT_RXD_N10 HT_TXD_N8 AD3 CPUCADOUTJ8
SYS_PWRGD 1 NB0CADOUTJ9 F4 HT_RXD_N9 HT_TXD_N7 R1 CPUCADOUTJ7
3 NB0CADOUTJ8 F5 U3 CPUCADOUTJ6
9 HTCPU_RST# 2
DY LDT_RST# 5
NB0CADOUTJ7 N2
HT_RXD_N8
HT_RXD_N7
HT_TXD_N6
HT_TXD_N5 U1 CPUCADOUTJ5
NB0CADOUTJ6 M1 HT_RXD_N6 HT_TXD_N4 W3 CPUCADOUTJ4
SSLVC08APWR-GP NB0CADOUTJ5 L2 HT_RXD_N5 HT_TXD_N3 AA3 CPUCADOUTJ3
7




NB0CADOUTJ4 K1 HT_RXD_N4 HT_TXD_N2 AA1 CPUCADOUTJ2
NB0CADOUTJ3 H1 HT_RXD_N3 HT_TXD_N1 AC3 CPUCADOUTJ1
R157
NB0CADOUTJ2 G2 HT_RXD_N2 HT_TXD_N0 AC1 CPUCADOUTJ0
1 2 NB0CADOUTJ1 F1 HT_RXD_N1
NB0CADOUTJ0 E2 HT_RXD_N0 HT_TXCLK_P1 Y4 CPUHTTCLKOUT1 CPUHTTCLKOUT1 9
0R0402-PAD HT_TXCLK_P0 Y1 CPUHTTCLKOUT0 CPUHTTCLKOUT0 9
NB0HTTCLKOUT1 J5 HT_RXCLK_P1
9 NB0HTTCLKOUT1 NB0HTTCLKOUT0 CPUHTTCLKOUTJ1
9 NB0HTTCLKOUT0 J3 HT_RXCLK_P0 HT_TXCLK_N1 Y3 CPUHTTCLKOUTJ1 9
+1.8V HT_TXCLK_N0 W1 CPUHTTCLKOUTJ0 CPUHTTCLKOUTJ0 9
NB0HTTCLKOUTJ1 K5 HT_RXCLK_N1
9 NB0HTTCLKOUTJ1 NB0HTTCLKOUTJ0 CPUHTTCTLOUT1
9 NB0HTTCLKOUTJ0 J2 HT_RXCLK_N0 HT_TXCTL_P1 T5 CPUHTTCTLOUT1 9
1




HT_TXCTL_P0 R2 CPUHTTCTLOUT0 CPUHTTCTLOUT0 9
C243 NB0HTTCTLOUT1
1 P3 HT_RXCTL_P1
SC1U10V3KX-3GP 9 NB0HTTCTLOUT1 NB0HTTCTLOUT0 CPUHTTCTLOUTJ1
N1 HT_RXCTL_P0 HT_TXCTL_N1 R5 CPUHTTCTLOUTJ1 9
2




9 NB0HTTCTLOUT0 CPUHTTCTLOUTJ0
U11B
14




HT_TXCTL_N0 R3 CPUHTTCTLOUTJ0 9
NB0HTTCTLOUTJ1 P4 HT_RXCTL_N1
9 NB0HTTCTLOUTJ1 NB0HTTCTLOUTJ0
9,36 HTCPU_PWRGD 4 9 NB0HTTCTLOUTJ0 P1 HT_RXCTL_N0
6 LDT_PWROK HTREF1 P6 L0_REF1 R89 44D2R2F-GP
1 2
B SYS_PWRGD 5
DY HTREF0 R6 L0_REF0 1 2