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8 7 6 5 4 3 2 1
INTEL (R) 850 CHIPSET
D
MS-6523 WILLAMETTE PROCESSOR SCHEMATICS
D
Title Page Title Page
Cover Sheet 1 PCI Connectors 21,22,23
Block Diagram 2,3,4,5 Audio 24,25,26
C C
Processor Sockets 6,7 CNR 27
Clock Synthesizer 8 LPC/Flopy Connector 28
DRCG 9 Hardware Monitor 29
MCH 10,11,12 Parallel Port/Serial Port 30
SCK/CMD 12 KeyBoard/Mouse Ports 31
RIMM 13,14 LAN 32
AGP Pro 15 Pull-up Resistors 33
ICH2 16,17 Front Pannel 34
FWH 18 VRM 9.0 35
B IDE Connectors 19 Voltage Regulator 36 B
USB Connectors 20 Diagnostic LED 37
Options
E: LXXXXD STANDARD
C: AUDIO (CODEC ONLY) T: AUDIO AMPLIFIER
D: DIAG. LED M: MSI STANDARD
A N: W/O 82562EM A
X: DEFAULT NOT STUFFED
Willamette Mother Board
Title
COVER
Size Document Number Rev
Custom MS-6523 1.0
Date: Wednesday, June 06, 2001 Sheet 1 of 38
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
14.318MHz SIO
14.318MHz SUSCLK
LAN_CLK FNT/LSB
CK00
33MHz PCI_Slot_5 EE_CLK LAN
3.3 volt 33MHz PCI_Slot_4 32.7kHz ICH
33MHz PCI_Slot_3 MS/KB
33MHz PCI_Slot_2 24.5MHz AUDIO CNR CON
33MHz PCI_Slot_1
CODEC
33MHz AUD_BCLK SMBCLK SMBCLK AUD_BCLK
AUDIO KBCLK
33MHz MCLK
33MHz
33MHz
C FWH C
33MHz
POC PLD GLUE
48MHz Pulled_up
3.3 volt
48MHz AGP CON SMBCLK HECETA
Hardware Management
66MHz HCLKOUT0
RCLKOUT0
66MHz HCLKOUT1
RCLKOUT1
66MHz MCH
66MHz DRCG1
DRCG2
3MREF_B 50/67MHz RIMM2
400MHz
Output RIMM0
3MREF 50/67MHz
3.3 volt MEM CLK DRCG_CTM*
14.318MHz DRCG_CTM1 SCL
SCL RIMM4
(Half Host CLK) RIMM1
B CPU B
100MHz CPU_CK
SMBCLK SCL
100MHz ITP_CK ITP Port SCL
Host Clock Pairs
100MHz MCH_CK
100MHz Pulled_up
A A
Title
Clock Distribution
Size Document Number Rev
CustomMS-6339 3.0
Date: Wednesday, June 06, 2001 Sheet 2 of 38
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
Power
Supply VRM Willamette Socket (SKT W) CK_SKS Clock
CONN
Scalable Bus Scalable Bus/2
AGP 4X 4X (266MHz) AGP Sync Clock (2) DRCG 1&2
AGP MCH: Memory 400MHz DIFF CLK
CONN 400MHz DIFF CLK
Controller HUB
VRM Direct RDRAM Channel A RIMM SKTS 1:2
AGP Direct RDRAM Channel B
CONN
RIMM SKTS 3:4
HUB Interface
C Heceta Hardware SM Bus C
Monitor PCI (33MHz)
ICH2: I/O
PCI Slots 1:5
Controller HUB
IDE CONN 1&2 AC '97
Digital
Central
LPC Bus AC Link
USB Port 1:3 CNR Riser
(Shared slot)
AC '97 Audio
USB Port 4 FWH: Firmware HUB AMP
FRNL Panel Codec
SMC I/O
Line Out
Tehama Chipset Telephone In
MIC In
Audio In
B LAN B
Line In
PS2 Mouse & Parallel (1) Floppy Disk Stuffing
Keyboard Serial (1) Drive CONN Options CD-ROM
RJ45
A A
Title
Block Diagram
Size Document Number Rev
CustomMS-6523 1.0
Date: Wednesday, June 06, 2001 Sheet 3 of 38
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D VCC12 VCORE D
INTERSIL 2-PHASE
CONVERTER >35A
SC1538 VCC1.8
VCC3
& MOSFET >4A
PSU
C
SC1538 VDDQ C
& MOSFET >2A
1.8VSB_STR
LT1087 0.8A
SC1536 3VSB_STR
& MOSFET >8A
2.5VSB_STR
EZ1580 7A
5VSB
SC1536 5VDUAL
& MOSFET 1.92A
VCC
B B
3VSB
SC1536
1.3A
& MOSFET
1.8VSB
0.8A
A A
Title
Reset/Power on Map
Size Document Number Rev
CustomMS-6523 1.0
Date: Wednesday, June 06, 2001 Sheet 4 of 38
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
AGP CK-SKS PROCESSOR RAMBUS CH1 ICH2 PCI Slots
Vcc3_CLK Vccp V_1P8_CMOS_CH1 Vcc3 Vcc3
+12V (3.3V) (3.3V)
(12V) (3.3V) (1.8V MAX.) (1.8V)
V_2P5_CH1 V_3P3_Stby +12V
(12V)
V_AGP_Vddq (2.5V Switched) (3.3V Standby)
(1.5V) DRCG_1 MCH
V_3P3_Stby V_1P8_core Vcc
V_1P8_core (5V)
FB_DRCG1_Vcc3 (3.3V Stanby) (1.8V)
Vcc (3.3V) (1.8V)
C (5V) V_1P8_Stby V_3P3_PCIVAUX C
V_AGP_Vddq RAMBUS CH2 (1.8V Standby) (3.3V Switched)
Vcc3 DRCG_2 (1.5V)
V_1P8_CMOS_CH2 V_3P0_BAT_Vreg
(3.3V) (3.3V Standby)
(Battery Switched)
(1.8V)
FB_DRCG1_Vcc3 Vccp
(3.3V) CNR CONN
(16.5V MAX.) V_2P5_CH2 V_5P0_Stby
FWH (2.5V Switched) (5V Standby) V_3P3_Stby
Audio 9708 (3.3VStandby)
PS2 CONN V_3P3_Stby Vccp
Vcc3
Vcc3 (3.3V Stanby) (1.65V MAX.) +12V
(3.3V)
Vreg_PS2 (3.3V) (12V)
(5V Switched)
Vcc RAMBUS TERM
(5V) Vcc
USB CONN (5V)
SIO
V_5P0_AUD_Analog V_1P8_Vterm_RIMM
Vreg_USB
(5V Analog) (1.8V) V_5P0_Stby
B Vcc3 (5V Switched) B
(3.3V) (5V Standby)
Audio 5880
V_3P3_Stby
(3.3 Standby) Vcc
(5V)
A A
Title
Power Distribution
Size Document Number Rev
CustomMS-6523 1.0
Date: Wednesday, June 06, 2001 Sheet 5 of 38
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VCCP
VCCP
VCC_SENS 35
R8
10 HA#[3..31] R88 49.9RST
VID[0..4] 28,37
VCCP
X_150
HA#31
HA#30
HA#29
HA#28
HA#27
HA#26
HA#25
HA#24
HA#23
HA#22
HA#21
HA#20
HA#19
HA#18
HA#17
HA#16
HA#15
HA#14
HA#13
HA#12
HA#11
HA#10
HA#9
HA#8
HA#7
HA#6
HA#5
HA#4
HA#3
VID4
VID3
VID2
VID1
VID0
R9 C5 C87 C6
R73
D 100RST 220P 220P 105P D
AW1
AU1
AV2
D12
C15
C11
C21
D22
C19
C17
D26
C27
D24
C25
C23
D28
C31
D30
C29
N39
R39
A11
A19
A13
A15
A21
A17
A29
A27
A23
A25
A31
F20
F22
F26
F28
F30
C1
49.9RST
A9
A1
A3
B4
B2
U6A
DBR
VID4#
VID3#
VID2#
VID1#
VID0#
VCC_SENSE
VSS_SENSE
ITP_CLK1
ITP_CLK0
A9#
A8#
A7#
A6#
A5#
A4#
A3#
A35#
A34#
A33#
A32#
A31#
A30#
A29#
A28#
A27#
A26#
A25#
A24#
A23#
A22#
A21#
A20#
A19#
A18#
A17#
A16#
A15#
A14#
A13#
A12#
A11#
A10#
10 HDBI#[0..3] HDBI#0 C64 C50 C65
AL39 DBI0#
HDBI#1 AU37 F14 R70
HDBI#2 DBI1# GTLREF3 220P 220P 105P
AT22 DBI2# GTLREF2 T36
HDBI#3 AW15 AP10 100RST
DBI3# GTLREF1
GTLREF0 AC35
C7 IERR#
D10 D6 BPM#5
MCERR# BPM5# BPM#4
16,33 FERR# P38 FERR# BPM4# C13
C5 E7 BPM#3
16 STPCLK# STPCLK# BPM3# BPM#2
F18 BINIT# BPM2# F10
D8 F12 BPM#1
16,18 HINIT# INIT# BPM1# BPM#0
C9 RSP# BPM0# F8
BPM#[0..5] 33
B34 F32 HREQ#4
10 HDBSY# DBSY# REQ4# HREQ#3
10 HDRDY# G37 DRDY# REQ3# D34
A35 F34 HREQ#2
10 HTRDY# TRDY# REQ2# HREQ#1
REQ1# D32
F36 C33 HREQ#0
10 HADS# ADS# REQ0#
C 10 HLOCK# A33 LOCK# C
10 HBNR# E35 BNR# HREQ#[0..4] 10
10 HIT# K36 HIT# TESTHI10 D20
D36 D18 R18
10 HITM# HITM# TESTHI9
10 HBPRI# L37 BPRI# TESTHI8 D16
10 HDEFER# J35 DEFER# TESTHI7 AW5
AU11 R89 4.7K
TESTHI6
33 TDI_CPU J39 TDI TESTHI5 AU9
TESTHI4 AU7
AT8 4.7K
TESTHI3 R17
38 TDO_CPU P36 TDO TESTHI2 AT6
TESTHI1 AT10 VCCP
TESTHI0 A7
D38 4.7K
38 TMS_CPU TMS
BCLK1# AP8 CPUCLK# 8
33 TRST#_CPU R35 TRST# BCLK0# AR7 CPUCLK 8
R37 U35 HRS#2
38 TCK_CPU TCK RS2# HRS#1
RS1# N35
H38 M36 HRS#0
28,29 VTIN2 THERMDA RS0#
28,29 VAGND E39 THERMDC HRS#[0..2] 10
33 THERMTRIP# U37 THERMTRIP# AP1# D14
AP0# F16
34 SKTOCC# A5 SKTOCC# BR0# B36 HBR#0 10,33
B
17,28,33 PROCHOT# F38 PROCHOT# B
M38 F24 R53
16 IGNNE# IGNNE# COMP1
16 SMI# K38 SMI# COMP0 AU27
T38 43.2RST
16 A20M# A20M R72 8/25 UPDATED
16,29 SLP# AW7 SLP# DP3# AT26
AT4 RESERVED DP2# AW27
DP1# AW35
AW9 AW33 43.2RST
17,33 CPU_PWRGD PWRGOOD DP0#
10,33 HCPURST# AW11 RESET# ADSTB1# G21 HADSTB#1 10
ADSTB0# G25 HADSTB#0 10
HD#63 AP12 AP16
D63# DSTBP3# HDSTBP#3 10
HD#62 AW17 AP20
D62# DSTBP2# HDSTBP#2 10
HD#61 AP14 AP30
D61# DSTBP1# HDSTBP#1 10
HD#60 AT12 AJ35
D60# DSTBP0# HDSTBP#0 10
HD#59 AU13 AP18
D59# DSTBN3# HDSTBN#3 10
HD#58 AW13 AP22
D58# DSTBN2# HDSTBN#2 10
HD#57 AT14 AP32
D57# DSTBN1# HDSTBN#1 10
HD#56 AU15 AG35
D56# DSTBN0# HDSTBN#0 10
HD#55 AT16
HD#54 D55#
AU17 D54# LINT1 W35 LINT1 16
LINT0 H36 LINT0 16
AT18 D53#
D52#
D51#
AU21D50#
AT20 D49#
AU19D48#
AU23D47#
D46#
AT24 D45#
D44#
AP28D43#
AU25D42#
AP24D41#
AT28 D40#
AT30 D39#
AU31D38#
D37#
AU33D36#
AP26D35#
AU29D34#
AT32 D33#
D32#
AL37 D31#
AT34 D30#
D29#
AU35D28#
AN35D27#
AT38 D26#
AR37D25#
AK36D24#
AN39D23#
AP36D22#
AU39D21#
AM38D20#
D19#
AP34D18#
AK38D17#
AT36 D16#
AA39D15#
AC37D14#
AJ37 D13#
AH36D12#
AD38D11#
AB36D10#
AE39D9#
W39 D8#
AF38 D7#
V36 D6#
AA35D5#
AG39D4#
AE37D3#
W37 D2#
AD36D1#
Y38 D0#
A
AW19
AW21
AW23
AW25
AW29
AW31
AW39
AW37
A
SOCKET423
Title
HD#53
HD#52
HD#51
HD#50
HD#49
HD#48
HD#47
HD#46
HD#45
HD#44
HD#43
HD#42
HD#41
HD#40
HD#39
HD#38
HD#37
HD#36
HD#35
HD#34
HD#33
HD#32
HD#31
HD#30
HD#29
HD#28
HD#27
HD#26
HD#25
HD#24
HD#23
HD#22
HD#21
HD#20
HD#19
HD#18
HD#17
HD#16
HD#15
HD#14
HD#13
HD#12
HD#11
HD#10
Willamette-CPU1
HD#9
HD#8
HD#7
HD#6
HD#5
HD#4
HD#3
HD#2
HD#1
HD#0
Size Document Number Rev
B MS-6523