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5 4 3 2 1
SM30 Block Diagram
Project code: 91.4BT01.001 SYSTEM DC/DC
TPS51125 50
PCB P/N : 48.4BT01.001 INPUTS OUTPUTS
Revision : 08239-SA 5V_S5(7A)
Crystal 3D3V_S5(7A)
DCBATOUT
D 14.318MHz SMSC PCB STACKUP 5V_AUX_S5 D
Mobile CPU EMC2103 TOP
3D3V_AUX_S5
Penryn 29
CLK GEN. VCC SYSTEM DC/DC
TPS51124 51
ICS 9LPRS929 S
4, 5
3 INPUTS OUTPUTS
HOST BUS 667/800/[email protected] S
1D05V_M(16A)
GND DCBATOUT
1D5V_S3(12A)
DDR3 Cantiga LCD BOTTOM
15 RT9026 52
800/1033 12,13
MHz AGTL+ CPU I/F
DDR_VREF_S3
DDR Memory I/F CRT 1.5V_S3 (1.2A)
17
DDR3 INTEGRATED GRAHPICS
LVDS, CRT I/F G9131 52
800/1033 12,13
MHz 6,7,8,9,10,11
C 3D3V_S0 2D5V_S0 C
X4 DMI Crystal (300mA)
C-Link0 25MHz
400MHz LAN TXFM RJ45 TPS51117 54
Crystal Giga LAN
32.768KHz BCM5764 DCBATOUT 1D8V_S0
Int MIC (9.4A)
Codec ICH9M PCIe CHARGER
15 AZALIA Mini Card (Robson2/3G) BQ24750 55
ALC272 6 PCIe ports
MIC In INPUTS OUTPUTS
30 PCI/PCI BRIDGE
32 ACPI 2.0
4 SATA Mini Card (WLAN) CHG_PWR
Kedron a/b/g/n 28 DCBATOUT
12 USB 2.0/1.1 ports 18V 6.0A
32 ETHERNET (10/100/1000MbE) LPC BUS
High Definition Audio CPU DC/DC
B
Line Out (SPDIF) LPC I/F ISL6266A B
Crystal 49
Serial Peripheral I/F
32.768KHz SPI BIOS LPC
Matrix Storage Technology(DO) KBC
Winbond
(2MB)
34
INPUTS OUTPUTS
Active Managemnet Technology(DO) DEBUG
WPCE773LA0DG CONN.34 DCBATOUT
VCC_CORE
OP AMP 33 0~1.3V
32 Launch
G1454 Buttom 38A
31 35 Daughter Board
INT.SPKR GFX DC/DC
1.5W 18,19,20,21
Touch INT. 08621 ISL6263
Pad 33 KB 33 53
SATA INPUTS OUTPUTS
USB Camera Launch Board
15 DCBATOUT
VCC_GFXCORE
HDD Mini USB 0~1.3V
SATA 23 Blue Tooth 6.5A
24
USB SM30
A A
ODD SATA 1 Port
Finger Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
22 Printer Taipei Hsien 221, Taiwan, R.O.C.
26 CardReader MS/MS Pro/xD
Title
Realtek /MMC/SD
27 5 in 1 27 BLOCK DIAGRAM
USB RTS5159 Size
A3
Document Number Rev
SM30 SB
2 Port 25 Date: Tuesday, October 28, 2008 Sheet 1 of 45
5 4 3 2 1
A B C D E
ICH9M Integrated Pull-up Cantiga chipset and ICH9M I/O controller
ICH9M Functional Strap Definitions Rev.1.5 page 92 Hub strapping configuration
ICH9 EDS 642879 and Pull-down Resistors Montevina Platform Design guide 22339
page 218
0.5
Signal Usage/When Sampled Comment ICH9 EDS 642879 Rev.1.5
HDA_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 Pin Name Strap Description Configuration
PCIE Port Config1 bit1, pulled low.When TP3 not pulled low at rising edge SIGNAL Resistor Type/Value
Rising Edge of PWROK of PWROK,sets bit1 of RPC.PC(Config Registers: CL_CLK[1:0] PULL-UP 20K CFG[2:0] FSB Frequency 000 = FSB1067
offset 224h). This signal has weak internal pull-down Select 011 = FSB667
CL_DATA[1:0] PULL-UP 20K 010 = FSB800
others = Reserved
4 HDA_SYNC PCIE config1 bit0,
Rising Edge of PWROK.
This signal has a weak internal pull-down.
Sets bit0 of RPC.PC(Config Registers:Offset 224h)
CL_RST0# PULL-UP 20K
CFG[4:3] Reserved
4
DPRSLPVR/GPIO16 PULL-DOWN 20K CFG8
GNT2#/ PCIE config2 bit2, This signal has a weak internal pull-up. CFG[15:14]
GPIO53 Rising Edge of PWROK. Sets bit2 of RPC.PC2(Config Registers:Offset 0224h) ENERGY_DETECT PULL-UP 20K CFG[18:17]
GPIO20 Reserved This signal should not be pulled high. HDA_BIT_CLK PULL-DOWN 20K
CFG5 DMI x2 Select 0 = DMI x2
GNT1#/ ESI Strap (Server Only) ESI compatible mode is for server platforms only. HDA_DOCK_EN#/GPIO33 PULL-UP 20K 1 = DMI x4 (Default)
GPIO51 Rising Edge of PWROK This signal should not be pulled low for desttop CFG6 iTPM Host 0= The iTPM Host Interface is enabled(Note2)
and mobile. HDA_RST# PULL-DOWN 20K Interface 1=The iTPM Host Interface is disalbed(default)
HDA_SDIN[3:0] PULL-DOWN 20K 0 = Transport Layer Security (TLS) cipher
Top-Block Sampled low:Top-Block Swap mode(inverts A16 for CFG7 Intel Management suite with no confidentiality
GNT3#/ Swap Override. all cycles targeting FWH BIOS space). HDA_SDOUT PULL-DOWN 20K engine Crypto strap 1 = TLS cipher suite with
GPIO55 Rising Edge of PWROK. Note: Software will not be able to clear the confidentiality (default)
Top-Swap bit until the system is rebooted HDA_SYNC PULL-DOWN 20K
0 = Reverse Lanes,15->0,14->1 ect..
without GNT3# being pulled down. GLAN_DOCK# The pull-up or pull-down active when configured for nativeCFG9 PCIE Graphics Lane 1= Normal operation(Default):Lane
GLAN_DOCK# functionality and determined by LAN controller Numbered in order
GNT0#: Boot BIOS Destination Controllable via Boot BIOS Destination bit GNT[3:0]#/GPIO[55,53,51] PULL-UP 20K
SPI_CS1#/ Selection 0:1. (Config Registers:Offset 3410h:bit 11:10). 0 = Enable (Note 3)
GPIO58 Rising Edge of PWROK. GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC. GPIO[20] PULL-DOWN 20K CFG10 PCIE Loopback enable 1= Disabled (default)
Integrated TPM Enable, Sample low: the Integrated TPM will be disabled. GPIO[49] PULL-UP 20K 00 = Reserve
Rising Edge of CLPWROK Sample high: the MCH TPM enable strap is sampled CFG[13:12] XOR/ALL 10 = XOR mode Enabled
SPI_MOSI low and the TPM Disable bit is clear, the LDA[3:0]#/FHW[3:0]# PULL-UP 20K 01 = ALLZ mode Enabled (Note 3)
Integrated TPM will be enable. 11 = Disabled (default)
LAN_RXD[2:0] PULL-UP 20K
3 DMI Termination Voltage, The signal is required to be low for desktop LDRQ[0] PULL-UP 20K
CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default) 3
Rising Edge of PWROK. applications and required to be high for
GPIO49 mobile applications. LDRQ[1]/GPIO23 PULL-UP 20K 0 = Normal operation(Default):
CFG19 DMI Lane Reversal Lane Numbered in Order
PME# PULL-UP 20K
1 = Reverse Lanes
PCI Express Lane Signal has weak internal pull-up. Sets bit 27 PWRBTN# PULL-UP 20K DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3)
SATALED# Reversal. Rising Edge of MPC.LR(Device 28:Function 0:Offset D8) DMI x2 mode[MCH -> ICH]:(3->0,2->1)
of PWROK. SATALED# PULL-UP 15K
SPKR No Reboot. If sampled high, the system is strapped to the SPI_CS1#/GPIO58/CLGPIO6 PULL-UP 20K Digital Display Port 0 = Only Digital Display Port
Rising Edge of PWROK. "No Reboot" mode(ICH9 will disable the TCO Timer (SDVO/DP/iHDMI) or PCIE is operational (Default)
system reboot feature). The status is readable SPI_MOSI PULL-DOWN 20K CFG20 Concurrent with PCIe 1 =Digital display Port and PCIe are
via the NO REBOOT bit. operting simulataneously via the PEG port
SPI_MISO PULL-UP 20K
0 =No SDVO Card Present (Default)
TP3 XOR Chain Entrance. This signal should not be pull low unless using SPKR PULL-DOWN 20K SDVO_CTRLDATA SDVO Present
Rising Edge of PWROK. XOR Chain testing. 1 = SDVO Card Present
TACH_[3:0] PULL-UP 20K
0 = LFP Disabled (Default)
GPIO33/ Flash Descriptor Sampled low:the Flash Descriptor Security will be TP[3] PULL-UP 20K Local Flat Panel
HDA_DOCK Security Override Strap overridden. If high,the security measures will be L_DDC_DATA (LFP) Present 1= LFP Card Present; PCIE disabled
_EN# Rising Edge of PWROK in effect.This should only be enabled in manufacturing USB[11:0][P,N] PULL-DOWN 15K
environments using an external pull-up resister. NOTE:
1. All strap signals are sampled with respect to the leading edge of
the (G)MCH Power OK (PWROK) signal.
2. iTPM can be disabled by a 'Soft-Strap' option in the
2 Flash-decriptor section of the Firmware. This 'Soft-Strap' is 2
activated only after enabling iTPM via CFG6.
Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time.
SMBus
SMBC_G792 Thermal
USB Table Media Key
USB KBC
Pair Device BAT_SCL
BATTERY
0 USB1(IO board)
1 USB1
2 CAMERA
3 MINIC2(WLAN)
4 NC
5 NC
SMB_CLK
6 FingerPrint LAN
1 ICH9M
SM30
1
7 BLUETOOTH
PCIE Routing 8 NC Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
LANE1 LAN BCM5764 9 USB2(HS) Taipei Hsien 221, Taiwan, R.O.C.
LANE2 MiniCard WLAN 10 MINIC1(IO BOARD) Title
SMBC_ICH CK505
LANE3 MiniCard(Robson2G/3G) 11 CARD READER Reference
Size Document Number Rev
A3
DDR
SM30 SB
Date: Thursday, December 04, 2008 Sheet 2 of 45
A B C D E
3D3V_S0
1201-SB
3D3V_S0
SMBC_ICH 12,13,21
1 R101 2 3D3V_48MPWR_S0 1 R119 2 3D3V_CLKPLL_S0
SMBD_ICH 12,13,21
1
1
1
2
0R0603-PAD C181 C180 C179 0R0603-PAD
SC4D7U6D3V3KX-GP
SC1U16V3ZY-GP
SCD1U16V2ZY-2GP
R102 0R2J-2-GP
2
1201-SB
2
2
2
R99
DY C200 DY
1
1
1
1
1
1
1
1
1
1
SC4D7U10V5ZY-3GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C198 C204 C171 C172 C196 C214 C215 C186
SC1U16V3ZY-GP
SC1U16V3ZY-GP
SC1U16V3ZY-GP
0R2J-2-GP
3D3V_48MPWR_S0
1
CL=20pF