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3DQDVRQLF
CONTENTS
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1. Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3. Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1. Control Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2. Video and Audio Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3. Power Supply Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4. Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1. Standby Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2. Power Supply Circuit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.3. Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.4. Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4.1.Overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4.2.Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.5. Secondary Supply Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5. Microprocessor and Teletext Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1. Microprocessor Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.1.Input Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.2.Output Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.3.Data Bus Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2. Teletext Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2.1.Teletext Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6. Memory (EEPROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7. Colour TV Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.1. V.I.F. Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.2. Video Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.3. Luminance Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.4. PAL Chrominance Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.5. SECAM Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.6. RGB Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.7. Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.8. Deflection Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.8.1.Horizontal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.8.2.Vertical Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8. Baseband Delay Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.1. Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9. SECAM Chrominance Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10. Horizontal Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
11. Vertical Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
11.1. Vertical Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
12. Beam Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
13. A.F. Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
14. Appendices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3DQDVRQLF
1. Introduction
We at Panasonic realise that the service engineer This Technical Guide contains information for Z7
needs to understand the circuitry inside the TV and chassis and should be used inconjunction with the
for this need, we have produced this Technical Guide. relevant Service Manuals for this chassis.
3DQDVRQLF
2. Features
The following features listed below are new to this model range which comprise of the following:
: New switch mode power supply with a 1 watt standby circuit
: New microprocessor, with built in teletext processing
: New one chip IC processing
: All alignments which are software controlled, except the Horizontal width for 21" (55cm) models
: Automatic Tuning Procedure (ATP) function
: New On Screen Display (OSD)
2.1. Differences
The major differences to Z5 are as follows:
: Low power consumption in standby (1watt)
: Power supply is switched off during standby mode
: Split DC supply used for the vertical output stage
: Improved circuit protection
: Software controlled alignments
CONTROL LINE BLOCK DIAGRAM
3DQDVRQLF
4. POWER SUPPLY
The mains A.C. voltage used for Z7 is fed via supply is then smoothed by capacitor C1203. This
connector E1 situated on the E-Board. From the rectified and smoothed supply is then again split into
connector E1 the mains A.C. power supply is fed via two paths.
the main TV On/Off switch S801 and two line
suppression filters L801 / L802 before being fed to the : The first path sees the supply voltage being fed
standby transformer T1201. via resistor R1247 to the standby relay RL1201 and
the relay winding to the collector of transistor Q1203.
At the standby transformer T1201 the A.C. supply Transistor Q1203 which is controlled by Q1202.
splits into two paths. Q1202 is responsible for switching the TV into and out
The first path sees the A.C. supply being fed to the of standby under the control of the microprocessor
normally open contact of the standby relay RL1201, IC1201 pin 1.
while the second path has the A.C. supply being fed
via the windings P2 / P1 of the standby transformer : The second path is via resistor R1246 to the
T1201 supply. base of transistor Q1204. This supply being regulated
by the zener diode D1209 is used as a base bias.
The second path from the standby transformer
4.1. Standby Power Supply Circuit T1201, that the supply voltage follows is via the
rectifying diode D1202 and smoothing capacitor
The standby transformer T1201 has the A.C. supply
C1201. Here the supply is applied to the collector of
as just mentioned being fed via the primary winding
Q1204. From the emitter of Q1204 a 5V standby
P2/P1.
supply is fed to the Microprocessor IC1201 and the
From the output of the secondary windings S2/S1 of
EAROM IC1205. This supply allows these circuits to
the standby transformer, a 5V standby supply is fed
operate during standby which is required to process
via resistor R1201, where the supply takes two paths.
the switch ON command from the remote control or
The first path that the standby supply follows is local keys, allowing the TV to be switched out of
via capacitor C1202 and rectifying diode D1208, this standby.
3DQDVRQLF
4.2. Power Supply Circuit Operation After the start up of the power supply unit the supply
voltage for IC801. is received from the auxiliary
The supply voltage for the main power supply circuit
winding B1 of transformer T801 which is fed via R807,
is fed via the standby relay RL1201 to the bridge
C808 to pin 2 of IC801 and internal transistor Q3.
rectifying diodes D801, D802, D803 and D804 where
The supply from B1 of the transformer T801 is
the A.C. voltage is full rectified and smoothed by
proportional to the supply fed via the primary winding
capacitor C807.
P2/P1. However winding B1 is unable to supply the
This smoothed d.c. voltage of approximately 300V necessary current to switch ON Q3 quickly and for
then follows two paths. this purpose transistor Q802 and capacitors C817,
C810 are used.
The first path feeds this d.c. supply to pin 3 of the
switched mode power supply IC IC801. Here the d.c.
voltage input via pin 3 is fed to the collector of internal At start-up Q3 begins to conduct as described above,
transistor Q3. with the conduction of Q3 the output from the auxiliary
winding B1 feeds back a positive supply to pin 2, as
The second path that the d.c. supply follows is via well as feeding this supply back to pin 2 the supply
resistors R804 and R811 and to pin 2 of IC801. This is also fed to the base of transistor Q802 via resistors
supply is used to provide IC801 with a start-up supply R813, R808. This supply biases Q802 into
which is fed to base of internal transistor Q3, conduction which results in capacitors C810 / C817
providing base bias. discharging via the collector - emitter junction to pin
With Q3 conducting the supply voltage flows via pins 2 and the base of Q3. The rate at which these
3 and 4 of IC801 via the primary winding P2/P1 of capacitors discharge being set by R809.
transformer T801, building up magnetic energy until
magnetic saturation is reached. This results in no
further supply voltage being fed via the windings When the transformer T801 finally reaches magnetic
P2/P1 where upon the magnetic field breaks down. saturation mentioned previously the output from the
winding B1 begins to reduce, with the reduction in
This break down of the magnetic field results in a supply from B1 winding the base bias to Q3 and Q802
transfer of energy from the primary winding to the are also reduced switching OFF both transistors.
secondary winding providing the required secondary With both transistors switched OFF capacitors C817
supplies. / C810 charge via D808.
The supply voltage flowing via the primary winding
P2/P1 is smoothed by C812 and fed to the horizontal When finally Q3 is switched on the cycle just
output stage. described is repeated.
3DQDVRQLF
4.3. Regulation When Q2 conducts the base bias of Q3 is reduced
keeping the output from pin 4 constant.
When the power supply has started and operating
normally any changes in load or mains supply voltage If however the load on the transformer T801
are regulated by auxiliary windings F1/F2 of T801. increases this demand has to be met and the effect
This is achieved by controlling the switching of Q1 on Q3 reduced. This is achieved by the negative
frequency of the power supply. feedback fed from the auxiliary winding F1/F2 to pin
To do this a negative feedback voltage is fed via 1 of IC801.
R810, L805 and diode D811 to pin 1 of IC801 Q1, this When an increase in current load occurs on T801 the
negative feedback voltage is then used to control the negative feedback voltage applied to pin 1 of IC801
bias of internal transistor Q1. will become more negative. The more negative the
feedback voltage becomes, the less Q1 and Q2
The internal transistor Q1 is biased On by the output
conduct enabling Q3 to conduct more.
supply fed from the emitter of internal transistor Q3.
This means that as the output from Q3 increases or A similar scenario occurs when the mains supply
decrease so does the bias of Q1. voltage decreases. Here the voltage from the emitter
If the output from Q3 increases Q1 conducts more, of Q3 also reduces which in turn reduces the effect Q1
this results in the base of Q2 becoming more negative and Q2 has on Q3, allowing Q3 to conduct more with
with respect to its emitter causing Q2 to conduct. the effect of stabilising the output at pin 4 of IC801.
3DQDVRQLF
4.4. Protection
4.4.1.Overcurrent bias of Q3 being removed. With no base bias on Q3
the output from pin 4 of IC801 is stopped.
The overcurrent protection circuit is made up of
resistor R805 and transistor Q801 which under The power supply will then initiate a repetitive rolling
normal operating conditions is switched Off. cycle for the purpose of an automatic restart, if
necessary.
However in the case of a short circuit an excessive
current demand will be placed on internal transistor 4.4.2.Overvoltage
Q3 which will result in an increased voltage drop
occurring across R805. The overvoltage protection circuit consists of zener
diode D812 which acts as a CROW BAR device.
This increased voltage drop across R805 will result in This works by creating a short circuit resulting in the
Q801 being biased into conduction, which in turn will overcurrent protection circuit described above being
bias On internal transistor Q2 resulting in the base activated.
4.5. Secondary Supply Side
On the secondary side, the supplies output from : 8V supply which is produced by IC853 is
transformer T801 are: used to supply IC201, IC601 and IC603.
103V (14") or 125V (21") this supply which is fed from : 5V supply produced by IC851 supplies
winding P1 of T801 is used to supply the line output IC601 and IC602.
stage. Finally all the above supplies are also monitored by
22V is used to supply the audio output IC IC251 the microprocessor IC1201 pin 31 for any short circuit
faults (described in Microprocessor section) which
12V is used to produce the following additional may occur.
supplies:
If the microprocessor detects a short circuit fault at
: 9V supply produced by IC852 and supplies the pin 31 then the microprocessor switches the TV into
tuner and IC601 standby.
3DQDVRQLF
5. MICROPROCESSOR AND TELETEXT PROCESSING
The microprocessor SDA5254 used on Z7 teletext : 256 bytes on-chip RAM
models, not only performs the required control
: 8kbytes on-chip display RAM
processing but also teletext processing which is
incorporated in the microprocessor, the processing of : 1 kbyte on-chip ACQ-buffer-RAM
which will be looked at later. First the control
processing stage of the microprocessor will be looked : 1 kbyte on-chip extended-RAM
at. : 6 channel 8 bit pulse Width Modulator
The elements that the microprocessor requires to
perform the aforementioned functions are: : 2 channel 14 bit Pulse Width Modulator
: 8 bit C500-CPU : 4 multiplexed ADC inputs with 8 bit resolution
: 18MHz internal clock : One 8 bit In/Out port with open drain and
operational I2C bus emulation
: Parallel 8-bit data and 16....19 bit address bus
: Two 8 bit pulse mutifunctional In/Out ports
: Eight 16 bit data pointer registers
: One 4 bit port works as either digital or
: Two 16 bit timers analogue input
: Watch-dog timers : One two bit In/Out port with optional functions
: Capture compare timer for infrared remote : One 3 bit In/Out port with optional RAM/ROM
control decoding address expansion up to 512Kbyte
: Serial Interface
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3DQDVRQLF
5.1. Microprocessor Stage the operation of this circuit being described in
section 11.1.
Input Information If a fault occurs resulting in one of the aforementioned
: Pins 5 - 9 - Local Keys supplies failing then pin 31 of the microprocessor
The local key commands are fed to the would become Low resulting in the TV being shut
microprocessor via pins 5, 6, 7, 8 and 9. These input down into standby by the microprocessor.
pins when not in use are held High via pull-up : Pin 32 - ABL (Automatic Beam Current
resistors which are connected to the 5V standby Limiter)
supply. The ABL input (pin 32 of the microprocessor) is used
: Pins 12/13 - XTAL1 / XTAL2 to switch the TV into standby in the event of excessive
The internal oscillator of the CPU is synchronised with beam current.
an external 18MHz quartz crystal X1201 which is When the TV is operating normally then any increase
connected to pins 12 and 13. in beam current is regulated by the Video Processing
The Clock frequencies for the I2C bus system are also IC IC601 pin 26, which is discussed in the Video
obtained from this frequency by internal dividing. Processing section. Pin 32 of the microprocessor is
held High via a pull-up resistor R1220 and the
: Pin 15 - Reset protection circuit does not operate.
During power On/Off operation, or during a fall in Where a fault occurs and the beam current continues
voltage to the microprocessor, incorrect operation to increase and exceeds the control of IC601, the
may occur. To prevent this incorrect operation the zener diode D506 would conduct as its anode would
microprocessor has a reset signal input via pin 15. become more negative with respect to its cathode,
This reset signal is provided by reset IC IC1202 pin due to the negative voltages being fed back from
1 which keeps the microprocessor in a stable T552 (Flyback Transformer). As a result of D506
condition until the voltage level has risen and has conducting pin 32 of the microprocessor would be
become stabilised. pulled Low, this would result in the TV then being
This reset IC which is fed a 5V standby supply is input switched into standby.
via pin 2 of IC1202. At switch On this supply is less
than 4.3V which results in the reset IC pulling pin 15 : Pin 33 - AFC
of the microprocessor Low keeping the During search mode the microprocessor detects the
microprocessor in a stable condition until the supply AFC voltage input via pin 33, which is fed from pin 1
voltage becomes greater than 4.3V at which time the of IC601 via Q102.
reset line goes High and the microprocessor begins When the AFC voltage reaches mid level between the
to operate. highest and lowest points of its swing, the
microprocessor stops the search operation and holds
: Pin 19 - AGC Detection the data.
This input signal which fed via buffer transistor Q23
is used only for U.K. models to detect the strongest : Pin 36 - Power Good (PG)
signals during auto tuning. This input terminal is used as a power OFF reset by
the microprocessor when the TV is switched into
: Pin 30 - CVBS standby. Without this power OFF reset the
This composite video signal which is input via pin 30 microprocessor has no way of knowing that the TV
is used for teletext processing which is carried out has been switched OFF into standby.
within the microprocessor. When the TV is switched OFF the operational data
: Pin 31 - Short Circuit Protection from the video processing IC is lost, this means that
Pin 31 of the microprocessor which is normally held at switch ON the data has to be reloaded back into the
High via R1218 is used to monitor the voltage supply video processing IC IC601.
lines for short circuit faults. The supply lines which are To be able to do this the microprocessor has to be
monitored are: reset so that at switch ON from standby the
microprocessor knows that it has to reload the
: 33V supply which is also monitored via R1218
required data.
: 22V supply is monitored by transistors Q252
and Q253, which under normal operating : Pin 44 - Remote IN
conditions are switched OFF. The commands required for control of the TV receiver
: 12V supply monitored via D857 are applied from the remote control.
: 9V supply monitored via D858 The command from the remote control transmitter is
: 8V supply monitored via D860 applied via RPM-637CBRS (remote control receiver)
: 5V supply monitored via D859 and Q1212 to pin 44 of IC1201, this command data
: The vertical output is protected by Q453 / Q454 being in serial format.
3DQDVRQLF
: Pin 45 - Sandcastle IN : Pin 16 - CATS On / Off
This input is used by the microprocessor for clamping The CATS Eye function described above can be
and synchronisation of the CVBS signal used for switched Off by the user if they so wish via the OSD.
teletext processing and display. The microprocessor pin 16 is responsible for this
control.
: Pin 46 - Slow Switching
Pin 46 of the microprocessor is used to automatically : Pin 20 - Off / Text
switch the TV to the 21 pin scart input terminal. This This output control line is used on teletext models
is achieved by a high level being applied via pin 8 of only. Here pin 20 of the microprocessor is fed to the
the 21 pin scart terminal which results in transistor base of transistor Q1214 where the control line splits
Q1240 conducting pulling pin 46 of the into two paths, the second path we will look at shortly.
microprocessor LOW. When this LOW level is
removed from pin 46 the TV switches out of the above The control line fed to the circuit made up of
mentioned mode. transistors Q1214 and Q1213 is used to control the
: Pin 52 - HFSW contrast level during Text operations
This output is used for Interlace Suppression, when During non teletext operations pin 20 of the
in teletext mode pin 46 of the microprocessor microprocessor is LOW, this results in Q1214
switches its output High or Low field by field. This conducting placing resistors R1290 and R1291 in
control line is then used to switch transistor Q1216 On parallel which sets the base bias of Q1213 and in turn
and Off. the base bias of transistors Q1207, Q1208, Q1209
When Q1216 is conducting the junction at resistors and setting the contrast level of the main picture and
R451 and R453 is effectively grounded, shorting out OSD displays.
R453 causing the picture to shift vertically. This
During teletext operations pin 20 of the
results in the two fields being super imposed on the
microprocessor goes HIGH this results in transistor
top of each other preventing text jitter.
Q1214 being switched Off removing R1290 out of the
parallel configuration with R1291. This changes the
5.1.2.Output Information base bias of Q1213 and the base bias of Q1207,
: Pin 1 - Standby Q1208 and Q1209. The result of this is to decrease
This output port of the microprocessor is used to the contrast level for teletext viewing.
control the switching of the TV in and out of standby.
This is achieved by controlling transistor Q1202. By The second path that was mentioned earlier sees the
applying a High level to the base of Q1202 this control line from pin 20 of the microprocessor being
transistor conducts and causes transistor Q1203 to fed from the base of Q1214 to the base of transistor
switch Off preventing current flow via the winding of Q1295. Transistor Q1295 along with Q1296 are used
standby relay RL1201, this causes the normal open to control the through put of the RGB signals from the
contact to open removing the mains A.C. supply from 21 pin scart socket via transistors Q3105, Q3106 and
mains power supply circuit. Likewise when a Low Q3107 to IC601.
level is fed to the base of Q1202 the transistor is
biased Off, thus allowing transistor Q1203 to conduct During non-teletex operation a LOW level from pin 20
by a High level which is applied via R1248. When of the microprocessor is applied to the base of Q1295
Q1203 conducts current via the standby relay causing the transistor to conduct. When Q1295
working coil causes the relay contact to close and conducts a High level is applied to the base of Q1296,
feeds the mains A.C. voltage to the power supply this biases Q1296 into conduction pulling the bases
circuit. of transistors Q3105, Q3106 and Q3107 LOW.
This LOW level which is applied to these 3 transistors
: Pin 4 - CATS Eye biases them into conduction allowing the RGB signals
Pins 4 of the microprocessor is used to control a to be fed to IC601 for further processing.
feature known as C.A.T.S. (Contrast Automatic
Tracking System). In teletext operation pin 20 of the microprocessor is
This is used to adjust the contrast level depending on HIGH. This HIGH level switches OFF Q1295 and in
the external light surrounding the TV. The level of turn Q1296 resulting in a HIGH level being applied via
adjustment made being dependant upon the mode R1296 to the base of the 3 transistors Q3105, Q3106,
selected (either Medium / Maximum). Q3107 forcing them into a non-conductive state.
The light sensed by the LDR (Light Dependant When the 3 transistors are in a non-conductive state
Resistor) R1223 is used to control the conduction of the RGB signals from the 21 pin scart socket are
transistor Q1217 which in in turn controls the voltage prevented from being applied to IC601, instead the
level at pin 26 of IC601 and thus the contrast level is teletext RGB signal from the microprocessor is
adjusted accordingly. applied to IC601.
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: Pin 21 - Coincidence Detection This mute control is used during channel change,
This output from the microprocessor is used to tuning and user mute operations.
ensure that the OSD display remains stable when the
: Pin 42 - F/AV
external sync. signal is poor or non-existent.
Pin 42 of the microprocessor is used on French
This is achieved by pin 21 of the microprocessor
models only. This control line is fed to switching IC201
outputing a High level to the base of Q303 which
pin 10, again only used in French Models, to switch
results in the Horizontal oscillator circuit of IC601 pin
AM sound and sound input via the AV terminal. (see
15 being modified by the addition of the filter circuit
section 14.5.)
made up of C319 and R320 being added into circuit.
: Pin 41 Pos/Neg_SC1/SC2
: Pin 22 - Message Received
Pin 41 of the microprocessor has two functions which
This output port, pin 22, is used to signal the user
it can perform. The first of these functions being used
when the TV has received a remote control signal by
for those models which can process different sound
flashing the standby LED.
carriers (i.e. 6.0MHz, 5.5MHz), here the SC1 and
The microprocessor via pin 22 outputs a pulsed signal
SC2 function would select either sound carrier 1 or 2.
which is used to switch transistor Q1201 On and Off
causing the standby LED to flash. The second function that pin 41 can perform is for
those models which are able to process SECAM L
: Pin 23 - Mute 2
signals. Here pin 41 of the microprocessor not only
The mute2 control line which is output from the
controls the sound carrier selection but also the
microprocessor pin 23 is fed to the audio output IC,
standards selection carried out in the I.F. stage.
IC251 pin 25, via transistor Q251.
: Pin 43 L'/L
During channel change, tuning and muting operations
Pin 43 of the microprocessor is used to select
a high level is output from pin 23 which causes Q251
between the two types of SECAM standards L/L', this
to conduct, this results in pin 5 of IC251 being pulled
control signal being fed via transistor Q22 to the I.F.
LOW resulting in the audio output being muted.
stage used on SECAM L models only.
: Pins 25 to 27 - FLT1, 2, 3
: Pins 47 to 49 - RGB Output
FLT3 pin 25 is used for the phase shifting of the VPS
The RGB signals output from the microprocessor are
or teletext data.
used to display the required teletext (text models
FLT2 pin 26 PLL filter for VPS slicing.
only) and OSD information on screen. The RGB
FLT1 pin 27 PLL filter is used by the teletext slicer.
signals being output from the following terminals:
: Pin 29 - IREF Blue - pin 49, Green - pin 48, Red - pin 47
This is a reference current output used by the vertical
: Pin 50 - Blanking
output stage of IC601.
The blanking pulse output from the microprocessor
: Pins 38 / 39 - Video Clock (V. CLK) pin 50 is used to provide the required switching
These connections are used to provide an external control for the teletext and OSD displays.
display clock reference frequency used for text
processing. Data Bus Lines
: Pin 40 - Mute 1 : Pins 2 / 3
The mute 1 control line output from pin 40 is used to The microprocessor communicates with the tuner,
mute the audio output via the 21 pin scart socket. EEPROM memory IC (IC1205) and Video Processor
The mute control line is fed via diode D1210 and IC601. Data on this bus line consists of serial data
R3130 to the emitter of Q3104. From the collector of (SDA) and clock signal (SCL). SDA being input and
Q3104 the mute control is applied to the base of the output from pin 2 and the SCL being output from
muting transistor Q3103. pin 3.
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5.2. Teletext Processing Stage
General Output from the slicer stage the sliced bit stream is
As already briefly mentioned earlier the fed to the Acquisition stage, where this bit stream is
microprocessor performs teletext processing as well converted into a byte stream and a framing code
as Control processing. To perform teletext processing check takes place to identify the TTX signal.
the following elements are required: After framing code detection a status word is
generated which is used to identify the type of data
: Teletext (TTX), Video Programme Signal received and the signal quality of the TV channel.
(VPS) slicer used to extract the relevant
information from the video signal. The text data is then fed via the dual port interface to
the buffer, where under the control of the CPU the
: Acquisition stage allowing simultaneous data is stored in the display RAM until the TTX data
reception of both the Teletext (TTX) and Video is required.
Programme Signal (VPS). The VPS feature is
not used. When the TTX data is requested the information is
read out of the Display RAM via the interface and fed
: Display Timing which is used to ensure that the to the Display Generator.
text information is locked to the same timing as The display generator then selects the pixel
the raster scan. information from the character ROM and translates it
: Character ROM which provides the required into RGB values.
characters for display of text information on
screen The character generator itself includes a character
and control decoder, a RAM interface, RGB and
: Display Generator used to create the Text Blanking signal generators.
display To allow the character generator to carry out
processing of the TTX signal, generation of a pixel
5.2.1.Teletext Operation clock is required.
This generation of the pixel clock is created internally
To enable teletext processing by IC1201 a CVBS by the display timing stage which is fed a sandcastle
signal is input via pin 30. Here the signal is fed to the pulse input via pin 45.
Teletext (TTX) slicer stage, where the horizontal and
vertical sync. information and TTX data are extracted The TTX data which has now been converted to RGB
from the CVBS signal. To do this the slicer has an values are then output from pins 47 (R), 48 (G), 49 (B)
analog circuit for sync. filtering and data slicing as well with the blanking signal being output via pin 50.
as an analog PLL used for system clock generation. These signals are then fed to the video processing IC
A third PLL is used to shift the system clock used for IC601 and are discussed in the Video Processing
data sampling of the TTX signal. section.
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6. Memory (EEPROM)
The memory IC is interfaced with the microprocessor Last Memory Information
via the I2C bus. The following data are memorised by
: Power on/off condition
the memory IC.
: Programme position
Service Data
: Volume level
: Picture Geometry adjustments
: Model features (option bytes) : Colour level
: Contrast level
Tuning data for 60 programme positions
: Brightness level
: Channel number
: SIF data SC1/SC2 : Sharpness level
: Colour system (PAL, SECAM or NTSC) : C-A-T-S mode
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7. COLOUR TV SIGNAL PROCESSING
General
TV signal processing on Z7 is carried out by IC601 : Composite video signal (Video input)
M52778SP.
This IC is responsible for the following processing: : Deflection Processing
: Video (V.I.F.)
Each of the aforementioned processing blocks will be
: Sound (S.I.F.) looked at in turn.
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7.1. Video (V.I.F) Processing
The I.F. signal required for V.I.F processing is fed Likewise for models with SECAM L and D/K
from the tuner, to pins 6 / 7 of IC601. processing L102 is used for n+1 processing. Control
of this circuit being carried out by IC1201 pin 41,
However for SECAM L models an additional I.F. stage which is fed to pin 1 of L102 adjusting the filtering
is used. This stage is responsible for the processing frequency depending on the standard being
of the VIF and SIF signals which for all other models processed.
are processed by the circuits described in the
following section (for the SECAM processing path The second path feeds the I.F. signal straight
see Appendices section 14.). to the SAW filter X101 pin 1 (or via Q101 where the
signal is buffered depending on the model). The
The I.F. signal for PAL processing is filtered via resulting V.I.F signal is then output via pins 4 and 5 of
L101 which is used as an adjacent channel trap ( n+1 X101, where the signal is input via pins 6 and 7 of
processing). IC601.
The V.I.F signal input via pins 6 and 7 is amplified by the highest and lowest points of its swing, the
a VIF amplifier before being output to the following microprocessor stops the search operation and
processing stages. At the output of the VIF amplifier maintains the data.
the video signal is split into two paths.
The second path that the video signal takes within
The first path feeds the video signal to the AFT stage IC601 is via the video detection stage, from here the
which is used to monitor the I.F. signal frequency. V.I.F. signal is fed to the VCO circuit whose reference
When the I.F. frequency is below 38.9MHz, the AFT frequency is set via pins 49 and 50. At the output of
voltage at pin 1 of IC601 rises, this voltage is fed to the VCO circuit a reference signal is fed back to the
AFC terminal of the tuner which causes the I.F. video detection stage.
frequency to rise by controlling the tuner's local The V.I.F. signal output from the video detection stage
oscillator and maintaining the I.F. signal frequency at is also fed to the I.F. AGC stage whose filter circuit is
38,9MHz. Likewise when the I.F. frequency is higher made up of C107 found at pin 4 of IC601 and used to
than 38.9MHz the AFT voltage at pin 1 of IC601 control the gain of the V.I.F. amplifier and keep the
reduces, again this voltage is fed to the AFC terminal correct signal output level.
of the tuner which causes the I.F. frequency to fall by The I.F. AGC circuit also feeds a signal to the RF AGC
controlling the tuners local oscillator and maintaining stage which outputs an AGC voltage via pin 3 of
the I.F. signal frequency at 38,9MHz. IC601. The R.F. AGC circuit monitors the RF signal
for any increase in signal level above the I.F. AGC
This AFT voltage output via pin 1 of IC601 is also fed
range and compensates for this change by controlling
to the microprocessor IC1201, which uses this
the gain of the RF amplifier in the tuner.
voltage during search mode. During search mode the
microprocessor detects the AFT voltage fed from pin Finally the VIF signal is output from pin 52 of IC601
1 of IC601 and transistor Q102 to pin 33 of the and fed via transistor Q301 where at its emitter the
microprocessor. signal splits into two paths, one for SIF processing
When the AFT voltage becomes mid level between and the other for video processing.
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The signal which is to be used for SIF processing is The first of these paths sees the video signal being
fed from the emitter of Q301 and applied to the base fed via the 100W resistor R3111 to the base of Q3101
of Q207. For video processing the signal again is fed where the signal is buffered. At its emitter the video
from the emitter of Q301 and is fed via resistor R310 signal is applied to the video out pin 19 of the 21 pin
where the signal is fed via filters X301 and X302 to the scart socket.
base of transistor Q302. The second path at the emitter of Q302 has the video
signal being fed via R314 (a 470W resistor) to the TV
At the base of transistor Q302 the video signal is fed
input terminal pin 36 of IC601.
via the base-emitter junction where the video signal
is buffered, at the emitter of Q302 the video signal is
split into two paths once again.
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7.2. Video Signal Processing 7.3. Luminance Processing
The video signal which is applied to an internal switch To process a PAL or SECAM luma signal, the video
of IC601 which is used to select between TV in pin 36 signal is fed via the chroma trap which filters out the
and an external video signal fed from the AV terminals chroma component from the video signal leaving only
to pin 34. The selected video signal output from the the luma component at its output.
switch then follows two paths. The luma signal is now fed to a delay line which
One path has the video signal being fed to the compensates for the processing time difference
Chroma trap for Luminance processing, while the between the the luma and chroma signals. From the
second path has the video signal being applied to the output of the delay line the next stage in the luma
High Pass Filter (HPF) stage for chroma processing. processing path is the video tone circuit which is
sharpness processing. The amount of sharpness
The video signal which is fed to the luminance applied to the luma signal being set by the user via the
processing path is applied to the chroma trap stage. OSD display.
At the input of the chroma trap the video signal splits Once the luma signal has undergone sharpness
into two paths. processing the luma signal is then fed via a clamp and
The one path feeds the video signal via a x2 amplifier video mute stage, before the signal is input to the
where the signal is output via pin 38, this signal is then RGB matrix stage where the RGB signals are
fed for sync. processing, here the signal is input back produced.
to IC601 via pin 39, while for SECAM chroma
processing the video signal is input to IC603.
The second path feeds the video signal via the
chroma trap for luminance processing.
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7.4. PAL Chrominance Processing place in the ID Detection stage, which then selects
the appropriate processing either PAL or SECAM.
To carry out chroma processing the video signal is fed
via the High Pass Filter (HPF) to the Automatic Colour The differential R-Y / B-Y signals output from the
Control (ACC) controlled amplifier. Here the signal is demodulator are fed via pins 41 and 43 to IC602.The
amplified and fed to the Band Pass Filter (BPF) which differential R-Y / B-Y signals are input to IC602 via
is used to remove the luma component from the pins 14 (R-Y) and 16 (B-Y). The signals are then
chroma signal. processed by this baseband delay line (discussed in
The chroma signal is then fed to a second amplifier the section 8.) before the signals are output from pins
circuit, this being controlled by the colour killer 11 (R-Y) / 12 (B-Y) and fed back to IC601 via pins 44
detection stage whose filter circuit consists of C601, (B-Y) / 45 (R-Y) for further processing.
R608 and R613 which can be found at pin 30. The
chroma signal output from the second amplifier then The R-Y / B-Y signals are then fed to the RGB matrix
splits into two paths. stage from the output of which the RGB signals are
The first path feeds the chroma signal to the split in to two paths.
demodulator stage which is controlled by the PAL The first path feeds the RGB signals to the Brightness
switch, here the differential R-Y and B-Y signals are control stage. Here the amount of brightness applied
produced. to the RGB signals is controlled by the user via the
The second path feeds the chroma signal to a number OSD display.
of control stages. Here the colour burst is used as a The second path feeds the RGB signals to the
reference signal. The colour burst which is exacted Automatic Contrast Limiting (ACL) stage. Here this
from the chroma signal is used as a control pulse for circuit is fed information from the CATS Eye circuit via
the APC (Automatic Phase Control) circuit. Q1217 as well as information used to guard against
Also fed to the APC stage is the VCO reference signal excessive beam current being drawn. Both input
of 4.43MHz which is set by X601 at pin 40. information which is fed via pin 26 of IC601 is then
In the APC stage (whose filter circuit you will find at used to control the level of contrast.
pin 35) the phase difference between the VCO Once the RGB signal is output from the brightness
reference signal and the colour burst signal is control stage, the signals are applied to the Drive
detected and output as a DC voltage. amplifier stage where the red drive and green drive
This DC voltage controls the reference signal which are set. The red and green drives being set via
is applied to the demodulator stage. software control which can be set in service mode.
During SECAM processing a reference signal is fed
from IC603 pin 1 to pin 42 of IC601. Here this signal The next control stage in the video processing path
is fed to the VCO stage adjusting the crystal is the clamp stage which is used to set the Cut-off for
controlled oscillator for SECAM processing. the RGB signals. Again the cut-off levels can be
adjusted in service mode. The RGB signals are then
The frequency of the burst is also used to identify the fed via the HV blanking stage before the RGB signals
current chroma carrier frequency which can then be are output via pins 21 (R), 22 (G), 23 (B) and fed to
used for automatic standards detection which takes the Y-Board and displayed on the CRT.
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7.5. SECAM Processing
To carry out SECAM processing as mentioned signals are input via pins 14 and 16. Again the
previously the video signal is output from pin 38 of processing of this IC is covered in a later section.
IC601 and fed via Q502 to pin 16 of IC603 which is However the processed SECAM chroma signal then
used to process the chroma component of the follows the same path as mentioned in the previous
SECAM video signal. PAL chroma processing stage.
SECAM chroma processing IC IC603 will be looked The luminance signal processing for SECAM is
at in section 9. Once the chroma signal has been carried out in the same way as previously described
processed the differential R-Y / B-Y signals are then in the PAL Luminance processing stage.
out via pins 9 and 10 of IC603. These signals are then
fed to IC602 the baseband delay line IC where the
7.6. RGB Input
IC601 via pins 25, 27 and 29 allows external RGB Teletext or OSD or from the 21 pin scart terminal.
signals to be input along with a fast blanking pulse These RGB signals are fed via the internal interface
input via pin 31 which is used for switching the internal to the RGB matrix, from here the external RGB
RGB interface. These RGB signals can be fed from signals then follow the previously described
either the Microprocessor IC1201 for display of processing path.
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7.7. Audio Processing line becomes HIGH resulting in Q203 switching ON
and D201 being switched OFF. Diode D202 however
The Colour TV Signal Processor IC601 is also
switches ON allowing filter X201 to be used for the
responsible for the processing of the audio signal.
required processing.
To carry out audio processing the V.I.F. signal output
via pin 52 is fed as mentioned previously via transistor This separated S.I.F. signal is then fed to pin 2 of
Q301 to the base of Q207. This V.I.F. signal is then IC601 to the internal amplifier and FM detector
fed via the S.I.F. filters X201 (6MHz) or X202 circuits. The FM detector circuit has two outputs.
(6.5MHz).
The selection between these S.I.F. filters is carried The first of these outputs is via pin 48 of IC601, this
out by the microprocessor pin 41 which is fed to feeds the audio signal to the 21 pin scart socket pins
resistor R210. At R210 the control line splits into two 1 and 3 via transistors Q201 / Q202.
paths. The second path feeds the audio signal via an internal
The first path sees the control line being fed via R210 switch which is used to switch between the internally
to the anode of diode D202, while the second path of processed audio signal and an external audio signal
the control line is fed via R212 to the base of Q203. fed from the AV terminals. The selected audio signal
is then fed to the following audio processing stage the
When the microprocessor pin 41 selects SC1 the Attenuation (ATT) circuit, this stage being
control line goes LOW. This low level results in D202 responsible for setting the gain of the audio signal
becoming non-conductive and Q203 being switched before the signal is fed to AF amplifier. The audio
OFF. With Q203 switched off diode D201 becomes signal which is output from the amplifier stage is then
conductive due to the HIGH level fed via R207 / R208, output via pin 46 and fed to the audio output IC IC251,
which allows X202 to be used for the required which will be described in section 13.
processing.
Likewise when SC2 (6MHz) is selected the control
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7.8. Deflection Processing allowing synchronisation of the horizontal sync
signal.
To carry out deflection processing the Luminance
signal is input via pin 39 of IC601 and is applied to the The horizontal sync signal is then fed via the
internal sync. separator, here the sync separator horizontal output stage, where the horizontal drive
slices the middle of the sync. pulse. Once the sync. pulse is output from IC601 via pin 13.
signal has been separated the signal is output via
The timing for the output of the horizontal drive pulse
three paths to :
is derived from the heater supply of the flyback
: Vertical sync. Separator transformer T552, this horizontal flyback pulse is fed
via a timing circuit to the base of Q503 before being
: Horizontal Divider
fed via Q504 and pin 12 of IC601 which has two
: AFC-1 functions.