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5 4 3 2 1




D D




C C




Sonoma Dothan EAL50_1
LA2362 Schematic
B B




A A




Security Classification Compal Secret Data
Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title
<br> THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL<br> Size Document Number Rev<br> AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D<br> DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2362 1<br> MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.<br> Date: Friday, March 11, 2005 Sheet 1 of 52<br> 5 4 3 2 1<br> 5 4 3 2 1<br><br><br><br><br> Compal confidential Block Diagram<br> Dothan<br>D Clock Generator D<br><br><br> uFCPGA CPU ICS<br><br><br> Memory<br> HA#(3..31) HD#(0..63) BUS(DDR) Fan Control X1<br> System Bus<br> 400 / 533MHz Dual Channel<br> CRT CONN. 2.5V 333MHz SO-DIMM X 1<br> BANK 0, 1<br> VGA & TV-OUT Alviso Intel 915 PM/GM SO-DIMM X 1 LED/B<br> BANK 2, 3<br> Board GMCH-M Channel A<br> Internal GM<br> ATI VGA 1257 FC-BGA SW LED BD<br> VGA CONN. PCI-E 16X<br><br>C<br> External PM C<br><br><br> T/P<br> DMI<br> 1.5V<br> MINI PCI 100MHz BT+MDC DC IN<br><br><br> 3.3V 24.576MHz AC-LINK BATT IN/+2.5V<br> 3.3V 33MHz PCI BUS 3.3V 33MHz<br> IDSEL:AD17<br> ICH6<br> (PIRQA/B#,GNT#2,REQ#2)<br> 609 BGA<br> RTL 8110SBL AC97 CODEC 1.5V/1.05V(+VCCP)<br> VIA6301 CardBus / G 8100CL / ATA100 RTL 250<br> 1394 Controller 100<br>B ENE CB712 B<br><br> 5V/3.3V/15V<br> HDD CDROM<br> Transformer<br> 1394 SDIO Slot 0 & RJ45 AMP &<br> CONN. CONN. LPC BUS<br> 3.3V 33MHz Phone/ MIC<br> USBPORT 0 Jack 1.8V / 0.9V<br> JUSBP2<br> USBPORT 1<br> JUSBP3<br> 48MHz / 480Mb USBPORT 2<br> USB2.0 BT<br> X BUS USBPORT 3 VCORE<br> JUSBP1<br> USBPORT 4<br> SIO JUSBP1<br> KB910 USBPORT 5<br> LPC47N217D RESERVED CHARGER<br> SST39VF080 USBPORT 6<br> RESERVED<br>A<br> USBPORT 7 A<br><br> RESERVED<br> FIR PIO Touch Pad Int.KBD<br><br> Security Classification Compal Secret Data<br> Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title<br> <Title><br> THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL<br> AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D<br> Size Document Number Rev<br> DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS CustomLA-2362 1<br> MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.<br> Date: Friday, March 11, 2005 Sheet 2 of 52<br> 5 4 3 2 1<br> 5 4 3 2 1<br><br><br><br><br> I2C / SMBUS ADDRESSING<br><br> External PCI Devices<br><br> DEVICE IDSEL # REQ/GNT # PIRQ PCB Rev Data<br><br> LAN AD17 0 F Bringup-Build 0.1<br> CARD BUS AD20 1 A SST-Build<br>D Power Managment table D<br> Cardreader B PT-Build<br> 1394 AD16 2 E<br> Wireless LAN(MINI PCI) AD18 3 G,H<br> ST-Build<br> Signal<br> +CPU_CORE<br> +VCCP QT-Build<br> +5VS<br> +3VS<br> State +2.5V +2.5VS<br> +12VALW +3V +1.8VS<br> +3VALW +5V +1.25VS<br> +5VALW +12V +1.5VS<br><br> @ Depop S0 ON ON ON<br><br> 1@ EAL51<br> S1 ON ON ON<br> 2@ EAL50 SCHEMATICS VERSION LIST<br> S3 ON ON OFF<br> 1@ EAL51 VALUE (DELETE SIO/1394) VERSION ISSUE DATE REMARK<br><br> S5 S4/AC ON OFF OFF<br> 0.0A First Release<br><br> S5 S4/AC don't exist OFF OFF OFF<br><br>C C<br><br><br><br><br> Ceramic Capacitor Spec<br> Guide:<br> Temperature Characteristics:<br> Symbol 0 1 2 3 4 5 6 7<br><br> CODE Z5U Z5V Z5P Y5U Y5V Y5P X5R X7R<br><br><br> 8 9 A B C D E F G<br><br> NP0 C0G BJ CH CJ CK SH SJ<br><br><br> H I J<br><br> UJ UK SL<br><br> Tolerance:<br> Symbol A B C D F G H J<br><br> CODE +-0.05PF +-0.1PF +-0.25PF +-0.5PF +-1PF +-2% +-3% +-5%<br><br>B B<br><br> K M N P Q V X Z<br><br> +-10% +-20% +-30% +100,-0% +30,-10% +20,-10% +40,-20% +80,-20%<br><br><br><br><br> SMBUS Control Table<br><br> THERMAL THERMAL VGA Thermal<br> SOURCE INVERTER BATT SERIAL SENSOR SENSOR SODIMM CLK CHIP MINI PCI LCD<br> EEPROM (CPU) (LM75) ADM1032<br><br><br> SMB_EC_CK1 PC87591L<br> SMB_EC_DA1<br><br> SMB_EC_CK2 PC87591L<br> SMB_EC_DA2<br><br> ICH_SMBCLK<br> ICH6-M<br> ICH_SMBDATA<br><br> LCD_DDCCLK Alviso<br>A LCD_DDCDATA GM-GP A<br><br><br><br><br> Security Classification Compal Secret Data<br> Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title<br> <Title><br> THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL<br> AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev<br> DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C LA-2362 1<br> MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.<br> Date: Friday, March 11, 2005 Sheet 3 of 52<br> 5 4 3 2 1<br> 5 4 3 2 1<br><br><br><br><br> ACIN<br> 32ms<br> +3/5/12VALW<br>D D<br><br><br><br><br> ON/OFF#<br> t<=10 ms<br> 8.5/2.44/3.792ms<br><br> EC_ON#<br> t=100 ms<br> 364us<br> t=109 ms<br> PWRBTN_OUT#<br> 438ms<br><br> SYSON<br> 3/5V 400us 2.5V(1.8ms)<br><br> +12/2.5/3/5V<br><br> 7.856ms<br>C RSMRST# t<110 ms C<br><br><br><br> 117ms<br><br> SLP_S3/4/5#<br> 92.88ms<br><br> SUSP# t>0<br><br> 1.25VS(104us) 1.5VS(2.64ms) 3VS(7.044ms) 5VS(10.26ms) 2.5VS(4.966ms)<br> +1.25/1.5/1.8/2.5/3/5VS<br> 2.166ms<br> 1.3ms PGD<br> +VCCP<br> 5.6ms<br> VR_ON#<br>B B<br> CPU_VID t<100 us<br><br> 726us<br> +CPU_CORE<br> 815.2us t<110 ms<br> Vgate<br> 99ms<br> SYSPOK<br> PCIRST/PLTRST# 1.036ms 2<t<3 RTCCLK<br><br> 61us<br><br> CPU_RST#<br>A A<br><br><br><br><br> Security Classification Compal Secret Data<br> Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title<br> <Title><br> THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL<br> Size Document Number Rev<br> AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D<br> DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2362 1<br> MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.<br> Date: Friday, March 11, 2005 Sheet 4 of 52<br> 5 4 3 2 1<br> 5 4 3 2 1<br><br><br><br><br> +3V<br> <8> H_A#[3..31] H_D#[0..63] <8><br> JCPU1A R79<br> 150_0402_5%<br><br> Dothan<br> H_A#3 P4 A19 H_D#0 1 2 ITP_DBRESET#<br> H_A#4 A3# D0# H_D#1<br> U4 A4# D1# A25<br> H_A#5 V3 A22 H_D#2<br> H_A#6 A5# D2# H_D#3<br> H_A#7<br> R3<br> V2<br> A6# D3# B21<br> A24 H_D#4<br> Test pad as closed as posible +VCCP<br> H_A#8 A7# D4# H_D#5 R90<br> W1 B26<br> H_A#9 A8# D5# H_D#6 54.9_0603_1%<br> T4 A21<br>D H_A#10 A9# D6# H_D#7 ITP_DBRESET# PAD T7 ITP_TDO D<br> W2 B20 1 2<br> H_A#11 A10# D7# H_D#8 R76<br> Y4 C20<br> H_A#12 A11# D8# H_D#9 ITP_BPM#0 PAD T6 54.9_0603_1%<br> Y1 B24<br> H_A#13 A12# D9# H_D#10 H_RESET#<br> U1 D24 1 2<br> H_A#14 A13# D10# H_D#11 ITP_BPM#1 PAD T8<br> AA3 E24<br> H_A#15 A14# D11# H_D#12 ITP_BPM#5<br> Y3 C26 1 2<br> H_A#16 A15# D12# H_D#13 ITP_BPM#2 PAD T10 R745 56_0402_5%<br> AA2 B23<br> H_A#17 A16# D13# H_D#14<br> AF4 E23<br> H_A#18 A17# D14# H_D#15 Place near JITP 0.5" ITP_BPM#3 PAD T9<br> AC4 C25<br> H_A#19 A18# D15# H_D#16<br> AC7 H23<br> H_A#20 A19# D16# H_D#17 ITP_BPM#4 PAD T12 +VCCP R479 39.4<br> AC3 G25<br> H_A#21 A20# D17# H_D#18 R74 37.4_0402_1%<br> AD3 A21# D18# L23<br> H_A#22 AE4 M26 H_D#19 22.6_0402_1% ITP_BPM#5 PAD T11 1 2 ITP_TMS<br> H_A#23 A22# D19# H_D#20 H_RESET# PAD T4 R85<br> AD2 A23# D20# H24 1 2<br> H_A#24 AB4 F25 H_D#21 ITP_TCK PAD T17 150_0402_5%<br> H_A#25 A24# D21# H_D#22 ITP_TDI<br> AC6 A25# ADDR GROUP DATA GROUP D22# G24 1 2<br> H_A#26 AD5 J23 H_D#23 R87 This shall place near CPU<br> H_A#27 A26# D23# H_D#24 22.6_0402_1% CLK_ITP_R PAD T19 R100<br> AE2 A27# D24# M23<br> H_A#28 AD6 J25 H_D#25 ITP_TDO 1 2 PAD T15 680_0402_5%<br> H_A#29 A28# D25# H_D#26 ITP_TRST#<br> AF3 A29# D26# L26 1 2<br> H_A#30 AE1 N24 H_D#27 R106<br> H_A#31 A30# D27# H_D#28 27.4_0402_1%<br> <8> H_REQ#[0..4] AF1 A31# D28# M25<br> H26 H_D#29 ITP_TRST# PAD T16 1 2 ITP_TCK<br> H_REQ#0 D29# H_D#30 ITP_TMS PAD T13<br> R2 REQ0# D30# N25<br> H_REQ#1 P3 K25 H_D#31 ITP_TDI PAD T14<br> H_REQ#2 REQ1# D31# H_D#32<br> T2 REQ2# D32# Y26<br> H_REQ#3 P1 AA24 H_D#33<br> REQ3# D33#<br> CLK_ITP_R# 1<br> R110 2 0_0402_5%<br> H_REQ#4 T1 REQ4# D34# T25<br> U23<br> H_D#34<br> H_D#35 Check ITP connector.<br> CLK_ITP_R 1<br> R112 H_ADSTB#0 D35# H_D#36<br> 2 0_0402_5% <8> H_ADSTB#0 U3 ADSTB0# D36# V23<br> @ H_ADSTB#1 AE5 R24 H_D#37<br> <8> H_ADSTB#1 ADSTB1# D37# H_D#38 +VCCP<br> @ D38# R26<br>C H_D#39 C<br> D39# R23<br> CLK_ITP @ R111<br> 1 2 0_0402_5% CPU_CK_ITP A16 AA23 H_D#40 1<br> <18> CLK_ITP CLK_ITP# ITP_CLK0 D40#<br> <18> CLK_ITP#<br> @ R109<br> 1 2 0_0402_5% CPU_CK_ITP# A15 ITP_CLK1 D41# U26 H_D#41 C359<br> V24 H_D#42<br> CLK_CPU_BCLK D42# H_D#43 0.1U_0402_10V6K<br> <18> CLK_CPU_BCLK B15 BCLK0 D43# U25<br> CLK_CPU_BCLK# B14 HOST CLK V26 H_D#44 2<br> <18> CLK_CPU_BCLK# BCLK1 D44#<br> Y23 H_D#45<br> D45# H_D#46<br> AA26<br> D46# H_D#47<br> Y25<br> H_ADS# D47# H_D#48<br> <8> H_ADS# H_BNR#<br> N2<br> ADS# D48#<br> AB25<br> H_D#49<br> Place near JITP<br> <8> H_BNR# L1 AC23<br> H_BPRI# BNR# D49# H_D#50<br> <8> H_BPRI# J3 AB24<br> H_BR0# BPRI# D50# H_D#51<br> <8> H_BR0# N4 AC20<br> H_DEFER# BR0# D51# H_D#52<br> <8> H_DEFER# L4 AC22<br> H_DRDY# DEFER# D52# H_D#53 +3VS<br> <8> H_DRDY# H2 AC25<br> H_HIT# DRDY# D53# H_D#54<br> <8> H_HIT# K3 AD23<br> H_HITM# HIT# D54# H_D#55<br> 56_0402_5% R78<br> <8> H_HITM# K4<br> HITM# CONTROL GROUP D55#<br> AE22<br> +VCCP<br> 1 2 H_IERR# A4 AF23 H_D#56<br> +VCCP IERR# D56#<br><br><br><br><br> 1<br> H_LOCK# J2 AD24 H_D#57<br> <8> H_LOCK# H_RESET# LOCK# D57# H_D#58<br> B11 AF20 R132<br> <8> H_RESET# RESET# D58# H_D#59<br> AE21 1K_0402_5%<br> D59# H_D#60<br> <8> H_RS#[0..2] AD21<br> H_RS#0 D60# H_D#61<br> H1 AF25<br><br><br><br><br> 2<br> RS0# D61#<br><br><br><br><br> 1<br> H_RS#1 K1 AF22 H_D#62<br> H_RS#2 RS1# D62# H_D#63 R124<br> L2 AF26<br> H_TRDY# RS2# D63#<br> <8> H_TRDY# M3 56_0402_5%<br> TRDY#<br> PROCHOT# <32><br> D25<br><br><br><br><br> 2<br> DINV0# H_DINV#0 <8><br><br><br><br><br> 1<br><br><br><br><br> <br/><br/><br/> <!-- Ezoic - Search Break Responsive - top_of_page --> <div id="ezoic-pub-ad-placeholder-110"> <script async src="https://pagead2.googlesyndication.com/pagead/js/adsbygoogle.js"></script> <!-- Preview Manual Leaderboard Responsive --> <ins class="adsbygoogle" style="display:block" data-ad-client="ca-pub-2156279550025329" data-ad-slot="6566435862" data-ad-format="auto" data-full-width-responsive="true"></ins> <script> (adsbygoogle = window.adsbygoogle || []).push({}); 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