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1 2 3 4 5
TW1 Block Diagram 1
CPU
Penryn
14.318MHz
478 PIN (micro FC-PGA) P3-4
A A
FSB 667 MHz(166X4)
FSB 800MHz(200X4)
FSB 1066MHZ(266X4)
CLOCK GEN
ICS9LPRS365
DVI
DVI UNBUFFERED P2
P23 DDRII 667/800 DDRII
Cantiga SODIMM
P11
LCD P7
LVDS GM45
1329 PIN (micro FCBGA) UNBUFFERED
34mm x 34mm DDRII 667/800 DDRII
CRT R/G/B
P10 P5-9 SODIMM
P11
DMI(4X)
Docking GLAN
P23 PCIE
Azalia Link
B WLAN Module B
PCIE
Intel 4965 P16
ICH9-M ALC262 MDC Module
P20 P21
RJ45 BOAZMAN 676 BGA
(Giga) PCIE 31mm x 31mm
(Intel Lan) P26
TI-TPA6011A4P21
P12-15 RJ11
R5C847 P17-18
1394+SD+MS+PCMCIA
PCI
Digital MIC*1
MIC. Jack Audio Jack INT.SPKR.
USB 1.1/2.0
3.3V LPC,33MHZ
P22 P22 P21 Knowles P20
SATA
SPI TPM 1.2
Infineon
Sinosun SSX35BCB P23
SPI BIOS(iAMT)
FeliCa P27 SATA HDD P24
C C
Docking*1P23 SATA ODD
PCU
P24
WPC775L
P19
USB Port *3
P24
SSD(TBD) P24
I2C
Fingerprint
P24 SPI LED
TOUCH PAD INT.K/B HDD Protection
BIOS Power/Speep/Bat ST Micro LIS3LV02DL
Bluetooth P25 P19
P16 3x,Digital,I2C
Wireless P24
T/P SWITCH
Camera P25 CAPS/NUM/SCRL
WLAN P16
SW
POWER
Wireless
S1
D MUTE D
QUANTA
COMPUTER
Size Document Number Rev
1.Level 1 Environment-related Substances Should NEVER be Used. 3E
2.Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as Green Partners.
TW1 Main Board
Date: Monday, April 28, 2008 Sheet 1 of 36
1 2 3 4 5
5 4 3 2 1
U1
2
C1 27P_4 CLK_XIN_365 3 X1 R_HCLK_CPU# RP1
CPUC0 60 3 4 0X2 HCLK_CPU# (3)
2
61 R_HCLK_CPU 1 2
CPUT0 HCLK_CPU (3)
Y1 R323
14.318MHZ/20P/20PPM 1M_4 57 R_HCLK_MCH# RP2 3 4 0X2
CPUC1_F HCLK_MCH# (5)
58 R_HCLK_MCH 1 2 Free Running when iAMT mode
HCLK_MCH (5)
1
R188 0_4 CLK_XOUT_365 CPUT1_F
2 X2
C2 27P_4 44 53
(14) PM_STPCPU# CPU_STOP# CPUC2_ITP/SRCC8
D (14) PM_STPPCI# 45 PCI_STOP# CPUT2_ITP/SRCT8 54 D
7 24 R_DREFSSCLK RP3 3 4 0X2
(11,14) PCLK_SMB_M SMBCLK 27MHz_NonSS/SRCT1/SE1 DREFSSCLK (5)
6 25 R_DREFSSCLK# 1 2
(11,14) PDAT_SMB_M SMBDAT 27MHz_SS/SRCC1/SE2 DREFSSCLK# (5)
63 20 R_DREFCLK RP4 3 4 0X2
(14) CLKEN CK_PWRGD/PD# DOTT_96/SRCT0 DREFCLK (5)
CLKUSB_48 R3 39/F_4 21 R_DREFCLK# 1 2
(14) CLKUSB_48 DOTC_96/SRCC0 DREFCLK# (5)
CPU_BSEL0 R4 2.21K/F_4 CLKUSB_48_R 17 USB_48MHz/FSLA R_PCIE_REQ_SATA# R7 475/F_4
SRCT3/CR#_C 31 PCIE_REQ_SATA# (14)
CPU_BSEL1 R5 0_4 64 32 R_PCIE_REQ_MINI# R6 475/F_4
FSLB/TEST_MODE SRCC3/CR#_D PCIE_REQ_MINI# (16)
CPU_BSEL2 R9 10K_4 14M_ICH_R 5 34 R_CLK_PCIE_MINI RP5 3 4 0X2
REF0/FSLC/TEST_SEL SRCT4 CLK_PCIE_MINI (16)
R8 33_4 35 R_CLK_PCIE_MINI# 1 2
(14) 14M_ICH SRCC4 CLK_PCIE_MINI# (16)
VCC3M_CK505 116mA
R10 0_6 4 47 R_CLK_PCIE_ICH# RP6 3 4 0X2
VCC3M_CLK VDDREF SRCC6 CLK_PCIE_ICH# (13)
C3 0.1U/10V_4 9 48 R_CLK_PCIE_ICH 1 2
VDDPCI SRCT6 CLK_PCIE_ICH (13)
C6 0.1U/10V_4 16
C4 C5 0.1U/10V_4 VDD48
23 VDD SRCC7/CR#_E 50
10U/6.3V_8 C8 0.1U/10V_4 46 51
C7 0.1U/10V_4 VDDSRC SRCT7/CR#_F
62 VDDCPU
C9 0.1U/10V_4 37 R_CLK_PCIE_MCH RP7 3 4 0X2
SRCT9 CLK_PCIE_MCH (5)
38 R_CLK_PCIE_MCH# 1 2
SRCC9 CLK_PCIE_MCH# (5)
R11 0_6 VCC1.05M_CLK 19 41 R_CLK_PCIE_LAN RP30 3 4 0X2
VCC1.05M VDD96_IO SRCT10 CLK_PCIE_LAN (23)
C12 0.1U/10V_4 27 42 R_CLK_PCIE_LAN# 1 2
VDDPLL3_IO SRCC10 CLK_PCIE_LAN# (23)
C11 0.1U/10V_4 33
C10 C14 0.1U/10V_4 VDDSRC_IO R_PCIE_REQ_MCH# R12 475/F_4
43 VDDSRC_IO SRCC11/CR#_G 39 PCIE_REQ_MCH# (5)
10U/6.3V_8 C13 0.1U/10V_4 52 40 R_PCIE_REQ_LAN# R74 475/F_4
VDDSRC_IO SRCT11/CR#_H PCIE_REQ_LAN# (23)
C16 0.1U/10V_4 56
C15 0.1U/10V_4 VDDCPU_IO R_CLK_PCIE_SATA RP8
C
SRCT2/SATAT 28 3 4 0X2 CLK_PCIE_SATA (12)
C
29 R_CLK_PCIE_SATA# 1 2
SRCC2/SATAC CLK_PCIE_SATA# (12)
8 R_PCLK_EC R13 33_4
PCI0/CR#_A PCLK_EC (19)
PCI1/CR#_B 10
11 R_PCLK_TPM R14 33_4
PCI2/TME PCLK_TPM (23)
1 12 R_PCLK_MP R16 33_4
GNDREF PCI3 PCLK_MP (16)
15 13 R_PCLK_cardbus R15 33_4
GNDPCI PCI4/27_Select PCLK_Cardbus (17)
18 14 R_PCLK_ICH R17 33_4
GND48 PCI_F5/ITP_EN PCLK_ICH (13)
22 GND
26 GND
30 GNDSRC Thermal PAD 65
36 VCC3M_CK505
GNDSRC
49 GNDSRC
59 55 PCIE_REQ_MINI# R19 10K_4
GNDCPU NC PCIE_REQ_SATA# R18 10K_4
PCIE_REQ_MCH# R20 10K_4
PCIE_REQ_LAN# R76 10K_4
ICS9LPRS365
R_PCLK_TPM R292 *10K_4
R2 10K_4
B B
CPU_BSEL0 R21 1K/F_4
(3) CPU_BSEL0 MCH_BSEL0 (5)
CPU_BSEL1 R22 1K/F_4
(3) CPU_BSEL1 MCH_BSEL1 (5)
CPU_BSEL2 R23 1K/F_4 R_PCLK_cardbus R24 10K_4
(3) CPU_BSEL2 MCH_BSEL2 (5)
R_PCLK_ICH R25 10K_4
27 Select ITP_EN(PIN14) PIN53/54
FSC FSB FSA Spread PIN 20/21 PIN 24/25
BSEL2 BSEL1 BSEL0 CPU SRC PCI REF USB DOT % PIN13 * 0 SRC8/SRC8#
1 ITP/ITP#
* 0 0 0 266.66 100 33.33 14.318 48 96 0.5 Down * 0 DOT_96 / DOT_96# LCDCLK / LCDCLK#
0 0 1 133.33 100 33.33 14.318 48 96 0.5 Down
1 SRC_0 / SRC_0# 27M / 27M_SS
0 1 0 200.00 100 33.33 14.318 48 96 0.5 Down
A A
0 1 1 166.66 100 33.33 14.318 48 96 0.5 Down
1 0 0 333.33 100 33.33 14.318 48 96 0.5 Down Byte0 Bit4: iAMT Enable/Disable Control
1 0 1 100.00 100 33.33 14.318 48 96 0.5 Down
QUANTA
1 1 0 400.00 100 33.33 14.318 48 96 0.5 Down
Title
COMPUTER
1 1 1 RESERVED CLOCK GENERATOR
1.Level 1 Environment-related Substances Should NEVER be Used. Size Document Number Rev
2.Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as Green Partners. 3E
TW1 Main Board
Date: Monday, April 28, 2008 Sheet 2 of 36
5 4 3 2 1
5 4 3 2 1
(5) H_A#[35..3]
H_A#3 J4
U2A
A[3]# ADS# H1 H_ADS# (5) VCCP
(5) H_D#[63..0] H_D#[63..0] (5)
3
ADDR GROUP_0
ADDR GROUP_0
H_A#4 L5 E2 U2B
A[4]# BNR# H_BNR# (5)
H_A#5 L4 G5 H_D#0 E22 Y22 H_D#32
A[5]# BPRI# H_BPRI# (5) D[0]# D[32]#
H_A#6 K5 H_D#1 F24 AB24 H_D#33
H_A#7 A[6]# H_D#2 D[1]# D[33]# H_D#34
M3 A[7]# DEFER# H5 H_DEFER# (5) E26 D[2]# D[34]# V24
DATA GRP 0
DATA GRP 0
H_A#8 N2 F21 R26 IERR : H_D#3 G22 V26 H_D#35
A[8]# DRDY# H_DRDY# (5) D[3]# D[35]#
DATA GRP 2
H_A#9 J1 E1 56_4 PU 56ohm , if no use. H_D#4 F23 V23 H_D#36
A[9]# DBSY# H_DBSY# (5) D[4]# D[36]#
H_A#10 N3 PU 68ohm.Serial R 2.2K,If use H_D#5 G25 T22 H_D#37
H_A#11 A[10]# H_D#6 D[5]# D[37]# H_D#38
P5 A[11]# BR0# F1 H_BREQ#0 (5) E25 D[6]# D[38]# U25
H_A#12 P2 H_D#7 E23 U23 H_D#39
A[12]# D[7]# D[39]#
CONTROL
H_A#13 L2 D20 H_D#8 K24 Y25 H_D#40
H_A#14 A[13]# IERR# H_D#9 D[8]# D[40]# H_D#41
D P4 A[14]# INIT# B3 H_INIT# (12) G24 D[9]# D[41]# W22 D
H_A#15 P1 H_D#10 J24 Y23 H_D#42
H_A#16 A[15]# H_D#11 D[10]# D[42]# H_D#43
R1 A[16]# LOCK# H4 H_LOCK# (5) J23 D[11]# D[43]# W24
M1 H_D#12 H22 W25 H_D#44
(5) H_ADSTB#0 ADSTB[0]# H_CPURST# (5) D[12]# D[44]#
C1 H_D#13 F26 AA23 H_D#45
RESET# H_RS#0 H_D#14 D[13]# D[45]# H_D#46
(5) H_REQ#0 K3 REQ[0]# RS[0]# F3 K22 D[14]# D[46]# AA24
H2 F4 H_RS#1 H_D#15 H23 AB25 H_D#47
(5) H_REQ#1 REQ[1]# RS[1]# D[15]# D[47]#
K2 G3 H_RS#2 J26 Y26
(5) H_REQ#2 REQ[2]# RS[2]# H_RS#[2..0] (5) (5) H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 (5)
(5) H_REQ#3 J3 REQ[3]# TRDY# G2 H_TRDY# (5) (5) H_DSTBP#0 H26 DSTBP[0]# DSTBP[2]# AA26 H_DSTBP#2 (5)
(5) H_REQ#4 L1 REQ[4]# (5) H_DINV#0 H25 DINV[0]# DINV[2]# U22 H_DINV#2 (5)
HIT# G6 H_HIT# (5) (5) H_D#[63..0] H_D#[63..0] (5)
H_A#17 Y2 E4
A[17]# HITM# H_HITM# (5)
H_A#18 U5 H_D#16 N22 AE24 H_D#48
H_A#19 A[18]# H_D#17 D[16]# D[48]# H_D#49
R3 A[19]# BPM[0]# AD4 K25 D[17]# D[49]# AD24
ADDR GROUP_1
H_A#20 W6 AD3 H_D#18 P26 AA21 H_D#50
H_A#21 A[20]# BPM[1]# H_D#19 D[18]# D[50]# H_D#51
U4 A[21]# BPM[2]# AD1 R23 D[19]# D[51]# AB22
H_A#22 Y5 AC4 H_D#20 L23 AB21 H_D#52
A[22]# BPM[3]# D[20]# D[52]#
XDP/ITP SIGNALS
DATA GRP 1
H_A#23 U1 AC2 H_D#21 M24 AC26 H_D#53
A[23]# PRDY# D[21]# D[53]#