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5 4 3 2 1
01
CPU_CORE1
ZK3 BLOCK DIAGRAM CPU_CORE2
CPU VDDNB_CORE
CPU CORE
PG 35
PCB STACK UP
LAYER 1 : TOP
+NB_CORE NB CORE LAYER 2 : GND
HOST 200MHz +1.35V_VDDHTTX (1.0~1.2V)
DDRII-SODIMM1 CPU_CLK LAYER 3 : IN1
AMD S1g2 CLOCK GENERATOR PG 36
PG 7,8 NBGFX_CLK
PCIE 100MHz LAYER 4 : IN2
DDR II 667 MHZ ICS9LPRS476AKLFT
D
Griffin Processor +2.5V +2.5V LAYER 5 : VCC D
USB 48MHz
NBGPP_CLK SLG8SP628VTR LAYER 6 : BOT
DDRII-SODIMM2 +1.5V +1.5V
RTM880N-795 REF 14MHz
PG 7,8 SBLINK_CLK
PG 3 +1.2V +1.2V
(638 S1g2 socket) Daughter Board
PG 4,5,6 +1.1V_NB
PG 38 MMB Board
HDMI HT_LINK +1.2V_S5
PG 20 AR8121(Giga) RJ45
PCI-E, 1X (port2)
+1.8VSUS +1.8VSUS
LVDS PG 21 PG 22 SMDDR USB Board
HDMI +1.8V
PG 19
LVDS(2ch) RX780/RS780M/RS780MC PCI-E, 1X (port0) +SMDDR_VTERM VTERM PG 37
Mini Card (WLAN)
USB2.0 (P3)
PG 23 Touch Pad board
+3VPCU
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CRT 21mm X 21mm, 528pin BGA
PG 19 PCI-E, 1X (port1) +3V_S5 3V/5V
CRT LVDS HDMI MINI CARD (TV)
+3VSUS
PG 23 Touch Pad board
+3V
C (with Fingerprinter) C
PCI-E X16 PG 9,10,11,12 PCI-E, 1X (port3) NEW CARD +5VPCU
MXM Module USB2.0 (P6) +5V
PG 18 PG 27 PG 34
A_LINK (X4) SBSRC_CLK
USB2.0 (P2/3) USB2.0 MINI CARD Ports X2
SATA - HDD1 SATA0 (MB) PG 23
PG 24 USB2.0 (P11) CCD USB2.0 (P0) USB2.0 I/O Ports X1
PG 19 (MB) PG 30
SB700
SATA - HDD2 SATA1
USB2.0 (P9) Fingerprint USB2.0 (P1) USB2.0 I/O Ports X1
PG 24 PG 31 (DB) PG 30
USB2.0 (P8) Card Reader USB2.0 (P7) USB2.0 I/O Ports X1
SATA - ODD SATA4 PG 28 (DB) PG 30
PG 24 USB2.0 (P5) Bluetooth USB2.0 (P4) USB2.0 I/O Ports X2
PG 22 (DB) PG 30
B B
E - SATA SATA2 21mm X 21mm, 528pin BGA
USB2.0 (P10) DOCKING
PG 31
PG 30 4.5W(Ext)
Azalia Azalia Audio Codec
4.3W(Int) ALC888 PG 25
PORT-A
PORT-B
MDC CONN MDC
RJ11 Speaker Amplifier
PG 13,14,15,16,17 Board
PCI ROUTING TABLE G1441R51U
Device IDSEL# REQ#/GNT# Interrupt
PG 25
PG 26
OZ129 AD17 REQ0# / GNT0# INTE#
LPC
H.P/ MIC INT. INT.
EC SPDIF JACK MIC S.P.
Digitally signed by dd WPCE775 PG 26 PG 26 PG 26 PG 26
A
DN: cn=dd, o=dd, PG 32
A
ou=dd, SPI
email=dddd@yahoo. Quanta Computer Inc.
com, c=US VR FAN Keyboard
Flash
ROM
Touch
Pad CIR Kill SW PROJECT : ZK3
Date: 2009.11.29 PG 23 PG 31 PG 31 PG 32 PG 31 PG 32 PG 32 Size Document Number
BLOCK DIAGRAM
Rev
1A
5
07:52:53 +07'00' 4 3 2
Date: Monday, August 18, 2008
1
Sheet 1 of 43
5 4 3 2 1
02
BD3G Power On Sequence BOM naming rule
From AC,Battery VIN
Items Function BTO Name Description
+5VPCU +3VPCU
D D
From PWM SYS_HWPG(PCU) 1 CIR v CIR@
From Power Button NBSWON# 2 HDMI port v HDM@
From EC S5_ON
3 HDMI transmitter v SI@ Silicon image SiI 1392/1932
+5V_S5
4 HDMI-CEC v CEC@ Renesas R8C/1B
+3V_S5
+1.2V_S5 5 Discrete VGA EV@ External VGA stuff
>10ms
From EC RSMRST# >100ms 6 UMA IV@ Internal VGA stuff
From EC DNBSWON#
7 New Card NEW@
From SB PCIE_WAKE#
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From SB to EC SUSB#,SUSC# SUSON 8 RJ11 v MD@ Modem
From EC SUSON 9 RJ45-10/100 40@ Marvell 8040T(10/100)
+3VSUS +1.8VSUS SMDDR_VREF SMDDR_VTERM
10 RJ45-1000 55@ Marvell 8055(Giga)
From PWM HWPG_1.8V (SUS) MAINON
C From EC MAINON 11 Option for RJ45-10/100 and RJ45-1000 40@55@ Option for 8040/8055 C
+5V +3V +2.5V +1.8V +1.5V +NB_CORE +1.1V_NB +1.35V_VDDHTTX 12 TV v TV@
From PWM HWPG_1.5V,HWPG_2.5V,GFXPG(MAIN) HWPG_1.2_NB
13 Cardbus CB@
From EC VRON
CPU_CORE0, CPU_CORE1, CPU VDDNB_CORE, +1.2V 14 FM transmitter v FM@
From PWM VRM_PWRGD (CPU) 15 Mainstream ID LED MID@
HWPG 16 Low cost ID LED LID@
From EC ECPWROK
17 CCD v CCD@
SB_PWRGD 0ns~30ns
NB_PWRGD 18 INT MIC v I_MIC@
99ms~108ms
From SB CPU_PWRGD 19 AMD Hyper Flash HF@ Only for AMD platform
From SB PLTRST# PCIRST#
20 North bridge(690MC/RS780MC) MC@ Only for AMD platform
From SB CPU_LDT_RST#
From SB CPU_LDT_STOP# 21 North bridge(RX780) RX@ Only for AMD platform
B B
22 PowerXpress PX@ Only for AMD platform
23 PowerXpress with UMA SKU PX@IV@ Only for AMD platform
24 PowerXpress with Discrete VGA SKU PX@EV@ Only for AMD platform
25 Power player/Power Shift PP@ Only for AMD platform
*Note: EC will sampling SUSB# & EC SMBUS Table
SUSC# every 5ms. Battery CPU thermal Sensor EC EEPROM VGA thermal Sensor Touch Sensor HDMI CEC
AMD SB700 SMBUS Table EC775 SDATA1/SCLK1(+3VPCU) V
CLK GEN RAM Mini Card (HD-Decoder) Mini-card(WL) New Card HDMI EC775 SDATA2/SCLK2(+3VPCU) V V
SB700 SDATA0/SCLK0(+3V) V V V V V EC775 SDATA3/SCLK3(+3VPCU) V V V
A A
SB700 SDATA1/SCLK1(+3V_S5) V EC775 SDATA4/SCLK4(+3VPCU)
SB700 SDATA2/SCLK2(+3V_S5) Power +3VPCU +3V +3VPCU +3V +3VPCU +5VPCU
Power +3V +3V +3V +3V (Atheros) +3V +3V_S5 Reserve MOS ckt X V X V X V
Reserve MOS ckt V V V V V V
Quanta Computer Inc.
PROJECT : ZK3
Size Document Number Rev
1A
SYSTEM INFORMATION
Date: Monday, August 18, 2008 Sheet 2 of 43
5 4 3 2 1
5 4 3 2 1
CLK_GEN_SLG8SP628 03
+3V +3V_CLK_VDD +1.2V +1.2V_CLK_VDDIO
L46 L47
BK1608HS600 BK1608HS600
C595 C593 C620 C589 C599 C616 C598 C591 C604 C592 C617 C594 C625 C590
C588 C587
D 22U/6.3V_8 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 22U/6.3V_8 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 D
ICS9LPRS480 P/N : Clock chip has internal serial terminations
for differencial pairs, external resistors are
SLG8SP628 P/N : AL8SP628000 reserved for debug purpose.
RTM880N-796 P/N : AL000880000
Place within 0.5"
of CLKGEN R528
U29
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*261/F_4
4 50 CPUCLKP_R RP43 1 2 0X2 CPUCLKP
+3V +3V_CLK_48 +3V_CLK_VDD VDDDOT CPUK8_0T CPUCLKP (4)
16 49 CPUCLKN_R 3 4 CPUCLKN To CPU
VDDSRC CPUK8_0C CPUCLKN (4)
L51 26
VDDATIG
35
VDDSB_SRC RS780/RX780 for VGA
BK1608HS600 40 30 NBGFX_CLKP_R RP44 1 2 0X2 NBGFX_CLKP
NBGFX_CLKP (11)
1
VDDSATA ATIG0T NBGFX_CLKN_R NBGFX_CLKN To NB
48 29 3 4 NBGFX_CLKN (11)
C615 VDDCPU ATIG0C RP45
55 28 MXM_REFCLKP_R 1 2 EV@0X2 CLK_MXM
CLK_MXM (18)
2.2U/6.3V_6 VDDHTT ATIG1T MXM_REFCLKN_R CLK_MXM# To MXM
56 27 3 4 CLK_MXM# (18)
2
VDDREF ATIG1C
63
VDD48
C SBLINK_CLKP_R RP41 C
37 1 2 0X2 SBLINK_CLKP
SBLINK_CLKP (11)
+1.2V_CLK_VDDIO SB_SRC0T SBLINK_CLKN_R SBLINK_CLKN To NB
11 36 3 4 SBLINK_CLKN (11)
+3V VDDSRC_IO0 SB_SRC0C RP42
17 32 SBSRC_CLKP_R 1 2 0X2 SBSRC_CLKP
SBSRC_CLKP (13)
VDDSRC_IO1 SB_SRC1T SBSRC_CLKN_R SBSRC_CLKN To SB
25 31 3 4 SBSRC_CLKN (13)
R254 *0_6 VDDATIG_IO SB_SRC1C
+3V_CLK_VDD 34
Q45 VDDSB_SRC_IO
47
VDDCPU_IO RX780 only
R522 *RHU002N06 22 NBGPP_CLKP_R RP47 1 2 *0X2 NBGPP_CLKP
NBGPP_CLKP (11)
2
SRC0T NBGPP_CLKN_R NBGPP_CLKN To NB
21 3 4 NBGPP_CLKN (11)
*10K_4 SRC0C CLK_PCIE_NEW_R RP48 0X2 CLK_PCIE_NEW_C
1 20 1 2 CLK_PCIE_NEW_C (27)
CLKREQ3# GND48 SRC1T CLK_PCIE_NEW#_R CLK_PCIE_NEW_C# To New Card
1 3 CLKREQ_TV# (23) 7 19 3 4 CLK_PCIE_NEW_C# (27)
GNDDOT SRC1C CLK_PCIE_MINI_R RP49 0X2 CLK_PCIE_MINI1
10 15 1 2 CLK_PCIE_MINI1 (23)
GNDSRC0 SRC2T CLK_PCIE_MINI#_R CLK_PCIE_MINI1# To Mini PCIE Slot
18 14 3 4 CLK_PCIE_MINI1# (23)
GNDSRC1 SRC2C CLK_PCIE_MINI2_R RP51 0X2 CLK_PCIE_TV
24
33
GNDATIG QFN64 SRC3T
13
12 CLK_PCIE_MINI2#_R
1
3
2
4 CLK_PCIE_TV#
CLK_PCIE_TV (23)
To Mini PCIE Slot
GNDSB_SRC SRC3C CLK_PCIE_TV# (23)
+3V 43 9 CLK_PCIE_LAN_R RP50 1 2 0X2 CLK_PCIE_LAN
GNDSATA SRC4T CLK_PCIE_LAN (21)
46 8 CLK_PCIE_LAN#_R 3 4 CLK_PCIE_LAN# To LAN Controller
GNDCPU SRC4C CLK_PCIE_LAN# (21)
52
Q44 GNDHTT
60
R521 *RHU002N06 GNDREF
42 T140
2
SRC6T/SATAT
41 T138
*10K_4 CG_XIN SRC6C/SATAC
61 6 T145
CLKREQ2# CG_XOUT X1 SRC7T/27M_SS
1 3 CLKREQ_WLAN# (23) 62 5 T144
X2 SRC7C/27M_NS
B:(10/25) Add WLAN & LAN CLKREQ circuit (BOI request) 2 54 NBHT_REFCLKP_R RP46 1 2 0X2 NBHT_REFCLKP
(7,14,20,21,23,27) PCLK_SMB SMBCLK HTT0T/66M NBHT_REFCLKP (11)
3 53 NBHT_REFCLKN_R 3 4 NBHT_REFCLKN To NB
(7,14,20,21,23,27) PDAT_SMB SMBDAT HTT0C/66M NBHT_REFCLKN (11)
R548 22_4
CLK_Card48 (28)
CLK_PD# 51 64 CLK_48M_USB_R R547 22_4 CLK_48M_USB To SB
PD# 48MHz_0 CLK_48M_USB (14)
T142 23 59 SEL_HTT66
B NEW_CLKREQ# CLKREQ0# REF0/SEL_HTT66 SEL_SATA B
(14,27) NEW_CLKREQ# 45
CLKREQ1# REF1/SEL_SATA
58 Ra
CLKREQ2# 44 57 SEL_27 R536 158/F_4 EXT_NB_OSC To NB
CLKREQ2# REF2/SEL_27 EXT_NB_OSC (11)
CLKREQ3# 39 R535 90.9/F_4
CLKREQ3#
T139 38
CLKREQ4#