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5 4 3 2 1
Enrico Caruso 14
D
Muxless/UMA Schematics Document D
Sandy Bridge
Intel PCH
2011-04-07
C C
REV : A00
DY : None Installed
UMA: UMA ONLY installed
PSL: KBC795 PSL circuit for 10mW solution installed.
B
10mW: External circuit for 10mW solution installed. B
DIS: MUXLESS solution installed.
Surge: For GO Rural config stuff.
GIGA: For GIGA LAN config stuff.
HDMI: For HDMI config stuff.
DIS_CRT: Pure DIS install
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Cover Page
Size Document Number Rev
A3
Enrico Caruso 14 A00
Date: Wednesday, April 13, 2011 Sheet 1 of 105
5 4 3 2 1
5 4 3 2 1
##OnMainBoard Block Diagram SYSTEM DC/DC
INPUTS
APL5916
OUTPUTS
48
CPU DC/DC
VT1316+1314
INPUTS OUTPUTS
42~44
VRAM gDDR3 900NHz
(Discrete/UMA co-lay) DCBATOUT 0D85V_S0 DCBATOUT
SYSTEM DC/DC
VCC_CORE
TPS51218 45
1GB (128Mx16x4) Project code: 91.4IU01.001 INPUTS OUTPUTS
4
512MB (64Mx16x4)
D
88,89,90,91
PCB P/N : 48.4IU16.0SC DCBATOUT 1D05V_VTT
D
gDDR3 Revision : 10315-SC SYSTEM DC/DC
TPS51125 41
900MHz Intel CPU INPUTS OUTPUTS
DDRIII 1066/1333 Channel A 5V_AUX_S5
DDRIII Slot 0 3D3V_AUX_S5
15 DCBATOUT 5V_S5
Sandy Bridge 1066/1333
Seymou-XT S3 PCIe x 8
3D3V_S5
15V_S5
(Discrete only)
DDRIII 1066/1333 Channel B DDRIII Slot 1 SYSTEM DC/DC
14 46
1066/1333 TPS51216R
83.84,85,86,87 INPUTS OUTPUTS
1D5V_S3
4,5,6,7,8,9,10 DCBATOUT 0D75V_S0
10/100 /1000 LOM RJ45 DDR_VREF_S3
PCIE x 1
Realtek RTL8111E (Giga LAN) CONN 59 GFX DC/DC
31 44
FDIx4x2 DMIx4 Realtek RTL8105E (10M/100M) VT1316+1317
C
1GB/s 802.11a/b/g INPUTS OUTPUTS C
PCIE x 1 Mini-Card DCBATOUT VCC_GFXCORE
WLAN+BT3.064
PCIE VGA
CRT CRT RT8208B 92
50
Intel 100MHz
INPUTS OUTPUTS
2.5Gbps
LCD LVDS
PCH USB 2.0 x 1 DCBATOUT VGA_CORE
49
Cougar Point TI CHARGER
BQ24707 40
HDMI HDMI 14 USB 2.0/1.1 ports USB 2.0 USB 2.0 x 1 CAMERA INPUTS OUTPUTS
51 49 +DC_IN_S5
ETHERNET (10/100/1000Mb) 480Mbps +PBATT DCBATOUT
High Definition Audio
SD/MMC/MS/ CardReader SATA ports (6) M/B
SYSTEM DC/DC
USB2.0 USB 2.0 x 1 APW7153B 47
MS Pro 74 Realtek PCIE ports (8) USB x1 (Left) 61
32 INPUTS OUTPUTS
RTS5138 LPC I/F
LPC Bus
B ACPI 1.1 3D3V_S5 1D8V_S0 B
33MHz USB 2.0 x 2 I/O board
Audio board Azalia USB x2 (Right) 82 SYSTEM DC/DC
AZALIA G9731 93
CODEC 24MHz 17,18,19,20,21,22,23,24,25 KBC INPUTS OUTPUTS
Internal Analog MIC
1D5V_S3 1V_VGA_S0
58
IDT 92HD87 NUVOTON 3D3V_S0 1D8V_VGA_S0
29 NPCE795BA0DX 27
Switches
INPUTS OUTPUTS
HP1 PS/2 PS/2
Thermal 1D5V_S3 1D5V_S0
82 5V_S5 5V_S0
ENE P2800
SPI
SATA
3Gbps
3D3V_S5 3D3V_S0
SATA
MIC IN 28
Touch Int.
PCB LAYER
PAD KB ENE P2793
L1:Top L4:Signal
2CH SPEAKER 69 69 Fan
28 L2:GND L5:VCC
Flash ROM L3:Signal L6:Bottom
58
A HDD ODD A
56 56 4MB 60
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Block Diagram
Size Document Number Rev
A3 A00
Enrico Caruso 14
Date: Wednesday, April 13, 2011 Sheet 2 of 105
5 4 3 2 1
A B C D E
PCH Strapping Huron River Schematic Checklist Rev.0_7 Processor Strapping Huron River Schematic Checklist Rev.0_7
Name Schematics Notes Pin Name Strap Description Configuration (Default value for each bit is Default
SPKR Reboot option at power-up 1 unless specified otherwise) Value
Default Mode: Internal weak Pull-down.
No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-k
- 10-k weak pull-up resistor.
CFG[2] PCI-Express Static 1: Normal Operation.
Lane Reversal 0: Lane Numbers Reversed 15 -> 0, 14 -> 1, ... 1
INIT3_3V# Weak internal pull-up. Leave as "No Connect".
Disabled - No Physical Display Port attached to
GNT3#/GPIO55 GNT[3:0]# functionality is not available on Mobile. CFG[4] 1: Embedded DisplayPort.
4 GNT2#/GPIO53 Mobile: Used as GPIO only
Enabled - An external Display Port device is
0 4
GNT1#/GPIO51 Pull-up resistors are not required on these signals. 0: connectd to the EMBEDDED display Port
If pull-ups are used, they should be tied to the Vcc3_3power rail.
CFG[6:5] PCI-Express 11 : x16 - Device 1 functions 1 and 2 disabled
Enable Danbury: Connect to Vcc3_3 with 8.2-k? weak pull-up resistor. Port Bifurcation 10 : x8, x8 - Device 1 function 1 enabled ;
SPI_MOSI function 2 disabled
Straps 11
Left floating, no pull-down required.
Disable Danbury: 01 : Reserved - (Device 1 function 1 disabled ;
function 2 enabled)
00 : x8, x4, x4 - Device 1 functions 1 and 2
Enable Danbury: Connect to +NVRAM_VCCQ with 8.2-kohm enabled
weak pull-up resistor [CRB has it pulled up
NV_ALE with 1-kohm no-stuff resistor] CFG[7] PEG DEFER TRAINING 1: PEG Train immediately following xxRESETB de assertion
1
Leave floating (internal pull-down) 0: PEG Wait for BIOS for training
Disable Danbury:
NC_CLE DMI termination voltage. Weak internal pull-up. Do not pull low.
Low (0) - Flash Descriptor Security will be overridden. Also, Voltage Rails
POWER PLANE VOLTAGE DESCRIPTION
when this signals is sampled on the rising edge of PWROK
then it will also disable Intel ME and its features. 5V_S0 5V
ACTIVE IN
SATA Table
HAD_DOCK_EN# High (1) - Security measure defined in the Flash Descriptor will be enabled. 3D3V_S0 3.3V
1D8V_S0 1.8V
/GPIO[33] Platform design should provide appropriate pull-up or pull-down depending on 1D5V_S0 1.5V SATA
3 the desired settings. If a jumper option is used to tie this signal to GND as 1D05V_VTT 1.05V
Pair Device
3
required by the functional strap, the signal should be pulled low through a weak 0D85V_S0 0.95 - 0.85V
0D75V_S0 0.75V
pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently. VCC_CORE 0.35V to 1.5V
Note: CRB recommends 1-kohm pull-down for FD Override. There is an internal VCC_GFXCORE 0.4 to 1.25V S0 0 HDD1
pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for 1D8V_VGA_S0 1.8V
3D3V_VGA_S0 3.3V CPU Core Rail 1 N/A
strapping functions. 1V_VGA_S0 1V Graphics Core Rail
2 N/A
HDA_SDO Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#. 3 N/A
5V_USBX_S3 5V
HDA_SYNC Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#. 1D5V_S3 1.5V S3 ODD
DDR_VREF_S3 0.75V
4
Low (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no 5 N/A
GPIO15 confidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher BT+ 6V-14.1V AC Brick Mode only
suite with confidentiality DCBATOUT 6V-14.1V
Note : This is an un-muxed signal. 5V_S5 5V All S states
5V_AUX_S5 5V
This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low. 3D3V_S5 3.3V
Sampled at rising edge of RSMRST#. 3D3V_AUX_S5 3.3V
CRB has a 1-kohm pull-up on this signal to +3.3VA rail.
3D3V_LAN_S5 3.3V WOL_EN Legacy WOL
GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down
GPIO8 using a 1k +/- 5% resistor. When this signal is sampled high at the rising edge of
RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is 3D3V_AUX_KBC 3.3V DSW, Sx ON for supporting Deep Sleep states
enabled.
2 Default = Do not connect (floating) 2
Powered by Li Coin Cell in G3
High(1) = Enables the internal VccVRM to have a clean supply for 3D3V_AUX_S5 3.3V G3, Sx and +V3ALW in Sx
GPIO27 analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board filter
circuits for analog rails.
USB Table SMBus ADDRESSES
PCIE Routing
Pair Device
I 2 C / SMBus Addresses HURON RIVER ORB
0 X LANE1 X
Device Ref Des Address Hex Bus
1 USB Ext. port 2 (MB) LANE2 LAN
2 X EC SMBus 1 BAT_SCL/BAT_SDA
Battery BAT_SCL/BAT_SDA
3 X CHARGER BAT_SCL/BAT_SDA LANE3 X
EC SMBus 2 SML1_CLK/SML1_DATA
4 X PCH LANE4 Wireless
SML1_CLK/SML1_DATA
eDP SML1_CLK/SML1_DATA
5 CARD READER
6 X
PCH SMBus
SO-DIMMA (SPD) PCH_SMBDATA/PCH_SMBCLK LANE5 X
SO-DIMMB (SPD) PCH_SMBDATA/PCH_SMBCLK
7 X PCH_SMBDATA/PCH_SMBCLK
1
Digital Pot
G-Sensor PCH_SMBDATA/PCH_SMBCLK LANE6 X DN15ATI Whistler
1
8 USB Ext. port 3 MINI PCH_SMBDATA/PCH_SMBCLK
PCH_SMBDATA/PCH_SMBCLK
9 USB Ext. port 1 LANE7 X Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
10 X Taipei Hsien 221, Taiwan, R.O.C.
LANE8 X
11 Mini Card1 (WLAN+BT) Title
12 CAMERA Table of Content
Size Document Number Rev
13 X A3
Enrico Caruso 14 A00
Date: Wednesday, April 13, 2011 Sheet 3 of 105
5 4 3 2 1
SSID = CPU
Signal Routing Guideline:
PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.
PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.
1D05V_VTT
CPU1A 1 OF 9
J22 PEG_IRCOMP_R R401 1 2 24D9R2F-L-GP
PEG_ICOMPI
Note:
19 DMI_TXN[3:0]
DMI_TXN0 B27
SANDY PEG_ICOMPO J21
H22
DMI_RX#0 PEG_RCOMPO
D Intel DMI supports both Lane DMI_TXN1
DMI_TXN2
B25
A25
DMI_RX#1 D
Reversal and polarity inversion DMI_TXN3 B24
DMI_RX#2
K33
but only at PCH side. This is DMI_RX#3 PEG_RX#0
19 DMI_TXP[3:0] PEG_RX#1 M35
enabled via a soft strap. DMI_TXP0 B28 DMI_RX0 PEG_RX#2 L34
DMI_TXP1 B26 J35
DMI_RX1 PEG_RX#3
DMI
DMI_TXP2 A24 J32
DMI_TXP3 DMI_RX2 PEG_RX#4
B23 DMI_RX3 PEG_RX#5 H34
19 DMI_RXN[3:0] PEG_RX#6 H31
DMI_RXN0 G21 G33
DMI_RXN1 DMI_TX#0 PEG_RX#7 PEG_RXN7
E22 DMI_TX#1 PEG_RX#8 G30 PEG_RXN7 83
DMI_RXN2 F21 F35 PEG_RXN6
DMI_TX#2 PEG_RX#9 PEG_RXN6 83
DMI_RXN3 D21 E34 PEG_RXN5
DMI_TX#3 PEG_RX#10 PEG_RXN5 83
E32 PEG_RXN4
19 DMI_RXP[3:0] PEG_RX#11 PEG_RXN4 83
DMI_RXP0 G22 D33 PEG_RXN3
DMI_TX0 PEG_RX#12 PEG_RXN3 83
DMI_RXP1 D22 D31 PEG_RXN2
DMI_TX1 PEG_RX#13 PEG_RXN2 83
PCI EXPRESS* - GRAPHICS
DMI_RXP2 F20 B33 PEG_RXN1
DMI_TX2 PEG_RX#14 PEG_RXN1 83
DMI_RXP3 C21 C32 PEG_RXN0
DMI_TX3 PEG_RX#15 PEG_RXN0 83
PEG_RX0 J33
PEG_RX1 L35
19 FDI_TXN[7:0] PEG_RX2 K34
FDI_TXN0 A21 H35
FDI_TXN1 FDI0_TX#0 PEG_RX3
H19 FDI0_TX#1 PEG_RX4 H32
Note: FDI_TXN2 E19 FDI0_TX#2 PEG_RX5 G34
FDI_TXN3 F18 G31
Intel(R) FDI
Intel FDI supports both Lane FDI0_TX#3 PEG_RX6
FDI_TXN4 B21 F33
Reversal and polarity inversion FDI_TXN5 C20
FDI1_TX#0 PEG_RX7
F30 PEG_RXP7
but only at PCH side. This is FDI1_TX#1 PEG_RX8 PEG_RXP7 83
FDI_TXN6 D18 E35 PEG_RXP6
FDI1_TX#2 PEG_RX9 PEG_RXP6 83
C enabled via a soft strap. FDI_TXN7 E17 FDI1_TX#3 PEG_RX10 E33
F32
PEG_RXP5
PEG_RXP4
PEG_RXP5 83
NOTE.
C
PEG_RX11 PEG_RXP4 83
D34 PEG_RXP3
19 FDI_TXP[7:0] FDI_TXP0 PEG_RX12 PEG_RXP2
PEG_RXP3 83 If PEG is not implemented, the RX&TX pairs can be left as No Connect