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5 4 3 2 1
SYSTEM DC/DC
Project code: 91.41601.001 TPS51125 50
PCB P/N : 48.4I601.011 INPUTS OUTPUTS
HOMA 3G Block Diagram
REVISION : -1 08204 5V_S5(7A)
3D3V_S5(7A)
DCBATOUT
5V_AUX_S5
3D3V_AUX_S5
SYSTEM DC/DC
D
Mobile CPU SMSC TPS51124 51 D
CLK GEN. EMC2102 INPUTS OUTPUTS
ICS 9LPRS365 Penryn 37
3 1D05V_S0(16A)
DCBATOUT
4, 5 LCD
15
Cable Dock Connector 1D8V_S3(16A)
RT9026 52
HOST BUS 667/800/[email protected]
CRT 4 Port USB 1.8V_S3
DDR_VREF_S3
18 (1.2A)
DDR2 Cantiga SWITCH CRT RJ45
667/800 MHz PI5C3257QE CRT/DVI-D G9131 52
12,13 AGTL+ CPU I/F HDMI
SWITCH 19
DDR Memory I/F DVI SPDIF/MIC in/Line in/Line out 3D3V_S0 2D5V_S0
(300mA)
PS8122QFN48G
DDR2 INTEGRATED GRAHPICS
LVDS, CRT I/F
AC Jack
PCIex16 RT9018 52
667/800 MHz
www.kythuatvitinh.com
VGA Borad 44
12,13 6,7,8,9,10,11 1D8V_S3 1D5V_S0
X4 DMI (MXM Connector) (2.5A)
C-Link0 46
400MHz CHARGER
MS/MS Pro/xD BQ24754 54
LINE IN
PCI CardBus /MMC/SD 31
5 in 1 INPUTS OUTPUTS
40 OZ711MZ030,31
C PCMCIA CHG_PWR C
Int MIC SLOT 35 DCBATOUT
18V 6.0A
40 Codec AZALIA ICH9M SPI BIOS
ALC268 6 PCIe ports CPU DC/DC
PCI/PCI BRIDGE 2M Bits 42 ISL6266A
38 49
ACPI 2.0 (DY)
MIC In INPUTS OUTPUTS
4 SATA
40
12 USB 2.0/1.1 ports VCC_CORE
DCBATOUT
ETHERNET (10/100/1000MbE) 0~1.3V
High Definition Audio 38A
LAN TXFM RJ45
OP AMP LPC I/F Giga LAN SWITCH 33 33 GFX DC/DC
40 LAN
G1454R Serial Peripheral I/F BCM5764MKMLG 32 PI3L500ZFEX ISL6263
Matrix Storage Technology(DO)
53
39
INT.SPKR Active Managemnet Technology(DO) New Card PWR SW INPUTS OUTPUTS
1.5W TPS2231 34
34
DCBATOUT
VCC_GFXCORE
40 0~1.3V
20,21,22,23
PCIe 6.5A
Line Out Mini Card 36
(Robson2/3G)
(No-SPDIF)
MODEM Mini Card (WLAN)
C Link1 Kedron a/b/g/n 36
B RJ11 MDC Card B
37 PCB STACKUP
LPC BUS
TOP
USB
SPI BIOS LPC VCC
SATA Mini USB KBC (2MB)
Winbond 42 S
HDD SATA Blue Tooth Camera DEBUG
26 WPCE773LA0DG CONN.42 S
25 41
Launch GND
SATA Finger USB Buttom
16 BOTTOM
ODD SATA
Printer 29 4 Port 28 Touch INT.
24 Pad 41 KB 41
USB
MIC in/Line-out/Line-in
Digitally signed by dd
A
DN: cn=dd, o=dd, A
ou=dd,
email=dddd@yahoo.
com, c=US
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Date: 2009.12.04
Title
BLOCK DIAGRAM
Size Document Number Rev
19:28:27 +07'00'
A2
HOMA 3G -1
Date: Friday, May 30, 2008 Sheet 1 of 56
5 4 3 2 1
A B C D E
ICH9M Integrated Pull-up Cantiga chipset and ICH9M I/O controller
ICH9M Functional Strap Definitions Rev.1.5 page 92 Hub strapping configuration
ICH9 EDS 642879 and Pull-down Resistors Montevina Platform Design guide 22339
page 218
0.5
Signal Usage/When Sampled Comment ICH9 EDS 642879 Rev.1.5
HDA_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 Pin Name Strap Description Configuration
PCIE Port Config1 bit1, pulled low.When TP3 not pulled low at rising edge SIGNAL Resistor Type/Value
Rising Edge of PWROK of PWROK,sets bit1 of RPC.PC(Config Registers: CL_CLK[1:0] PULL-UP 20K CFG[2:0] FSB Frequency 000 = FSB1067
offset 224h). This signal has weak internal pull-down Select 011 = FSB667
CL_DATA[1:0] PULL-UP 20K 010 = FSB800
others = Reserved
4 HDA_SYNC PCIE config1 bit0,
Rising Edge of PWROK.
This signal has a weak internal pull-down.
Sets bit0 of RPC.PC(Config Registers:Offset 224h)
CL_RST0# PULL-UP 20K
CFG[4:3] Reserved
4
DPRSLPVR/GPIO16 PULL-DOWN 20K CFG8
GNT2#/ PCIE config2 bit2, This signal has a weak internal pull-up. CFG[15:14]
GPIO53 Rising Edge of PWROK. Sets bit2 of RPC.PC2(Config Registers:Offset 0224h) ENERGY_DETECT PULL-UP 20K CFG[18:17]
GPIO20 Reserved This signal should not be pulled high. HDA_BIT_CLK PULL-DOWN 20K
CFG5 DMI x2 Select 0 = DMI x2
GNT1#/ ESI Strap (Server Only) ESI compatible mode is for server platforms only. HDA_DOCK_EN#/GPIO33 PULL-UP 20K 1 = DMI x4 (Default)
GPIO51 Rising Edge of PWROK This signal should not be pulled low for desttop CFG6 iTPM Host 0= The iTPM Host Interface is enabled(Note2)
and mobile. HDA_RST# PULL-DOWN 20K Interface 1=The iTPM Host Interface is disalbed(default)
HDA_SDIN[3:0] PULL-DOWN 20K 0 = Transport Layer Security (TLS) cipher
Top-Block Sampled low:Top-Block Swap mode(inverts A16 for CFG7 Intel Management suite with no confidentiality
GNT3#/ Swap Override. all cycles targeting FWH BIOS space). HDA_SDOUT PULL-DOWN 20K engine Crypto strap 1 = TLS cipher suite with
GPIO55 Rising Edge of PWROK. Note: Software will not be able to clear the confidentiality (default)
Top-Swap bit until the system is rebooted HDA_SYNC PULL-DOWN 20K
0 = Reverse Lanes,15->0,14->1 ect..
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without GNT3# being pulled down. GLAN_DOCK# The pull-up or pull-down active when configured for nativeCFG9 PCIE Graphics Lane 1= Normal operation(Default):Lane
GLAN_DOCK# functionality and determined by LAN controller Numbered in order
GNT0#: Boot BIOS Destination Controllable via Boot BIOS Destination bit GNT[3:0]#/GPIO[55,53,51] PULL-UP 20K
SPI_CS1#/ Selection 0:1. (Config Registers:Offset 3410h:bit 11:10). 0 = Enable (Note 3)
GPIO58 Rising Edge of PWROK. GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC. GPIO[20] PULL-DOWN 20K CFG10 PCIE Loopback enable 1= Disabled (default)
Integrated TPM Enable, Sample low: the Integrated TPM will be disabled. GPIO[49] PULL-UP 20K 00 = Reserve
Rising Edge of CLPWROK Sample high: the MCH TPM enable strap is sampled CFG[13:12] XOR/ALL 10 = XOR mode Enabled
SPI_MOSI low and the TPM Disable bit is clear, the LDA[3:0]#/FHW[3:0]# PULL-UP 20K 01 = ALLZ mode Enabled (Note 3)
Integrated TPM will be enable. 11 = Disabled (default)
LAN_RXD[2:0] PULL-UP 20K
3 DMI Termination Voltage, The signal is required to be low for desktop LDRQ[0] PULL-UP 20K
CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default) 3
Rising Edge of PWROK. applications and required to be high for
GPIO49 mobile applications. LDRQ[1]/GPIO23 PULL-UP 20K 0 = Normal operation(Default):
CFG19 DMI Lane Reversal Lane Numbered in Order
PME# PULL-UP 20K
1 = Reverse Lanes
PCI Express Lane Signal has weak internal pull-up. Sets bit 27 PWRBTN# PULL-UP 20K DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3)
SATALED# Reversal. Rising Edge of MPC.LR(Device 28:Function 0:Offset D8) DMI x2 mode[MCH -> ICH]:(3->0,2->1)
of PWROK. SATALED# PULL-UP 15K
SPKR No Reboot. If sampled high, the system is strapped to the SPI_CS1#/GPIO58/CLGPIO6 PULL-UP 20K Digital Display Port 0 = Only Digital Display Port
Rising Edge of PWROK. "No Reboot" mode(ICH9 will disable the TCO Timer (SDVO/DP/iHDMI) or PCIE is operational (Default)
system reboot feature). The status is readable SPI_MOSI PULL-DOWN 20K CFG20 Concurrent with PCIe 1 =Digital display Port and PCIe are
via the NO REBOOT bit. operting simulataneously via the PEG port
SPI_MISO PULL-UP 20K
0 =No SDVO Card Present (Default)
TP3 XOR Chain Entrance. This signal should not be pull low unless using SPKR PULL-DOWN 20K SDVO_CTRLDATA SDVO Present
Rising Edge of PWROK. XOR Chain testing. 1 = SDVO Card Present
TACH_[3:0] PULL-UP 20K
0 = LFP Disabled (Default)
GPIO33/ Flash Descriptor Sampled low:the Flash Descriptor Security will be TP[3] PULL-UP 20K Local Flat Panel
HDA_DOCK Security Override Strap overridden. If high,the security measures will be L_DDC_DATA (LFP) Present 1= LFP Card Present; PCIE disabled
_EN# Rising Edge of PWROK in effect.This should only be enabled in manufacturing USB[11:0][P,N] PULL-DOWN 15K
environments using an external pull-up resister. NOTE:
1. All strap signals are sampled with respect to the leading edge of
the (G)MCH Power OK (PWROK) signal.
2. iTPM can be disabled by a 'Soft-Strap' option in the
2 Flash-decriptor section of the Firmware. This 'Soft-Strap' is 2
activated only after enabling iTPM via CFG6.
Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time.
1 1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reference
Size Document Number Rev
A3
HOMA 3G -1
Date: Friday, May 30, 2008 Sheet 2 of 56
A B C D E
1D05V_S0 R262 3D3V_S0
2 1 3D3V_S0
3D3V_S0 0R0603-PAD
3D3V_CLKGEN_S0 2 R263 1
1 R224 2 3D3V_48MPWR_S0 3D3V_CLKPLL_S0 2 R264 1 0R0603-PAD
1
1
1
1
1
1
SC4D7U10V5ZY-3GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
0R0603-PAD 0R3-0-U-GP C339 C326 C310 C311 C338 C318
1
1
1
1
1
1
1
1
1
SC4D7U10V5ZY-3GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C303 C304 C332 C317 C331 C333 C337 C327 C328 DY
SC4D7U6D3V3KX-GP
SC1U16V3ZY-GP
DY 08/5/23 -1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4 4
3