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A B C D E
1 1
Compal Confidential
2
Schematics Document 2
INTEL Auburndale BGA with IBEX core logic
Swatch UMA
LA-5251P
3 3
2010-01-04
REV:0.9
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/09/15 Deciphered Date 2010/12/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5251P 0.9
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 05, 2010 Sheet 1 of 47
A B C D E
A B C D E
Compal Confidential
File Name : LA-5251P Swatch UMA XDP Conn.
Page 4
Accelerometer
LIS302DLTR
PEG-eDP
Mobile Page 24
1
Display port panel 1
Page 20
Auburndale CPU DDR3 1066/1333MHz 1.5V DDR3-SO-DIMM X 2 Fan Control
BANK 0, 1, 2, 3 Page 9,10 Page 4
BGA 1288pins
Dual Channel
RGB Thermal Sensor
Page 4,5,6,7,8
VGA EMC2113 Page 4
Page 18
DP *1(Docking)
Page 29
Display port DDI_D FDI DMI X4 CK505
Page 18
USB *1(Docking)Page Clock Generator
29
SLG8SP585VTR
DDI_B USB conn*1(Left side)
Page 11
DDI Page 24
2 Express Card 54 WWAN USB2.0 2
+SIM Card
USB2.0 FingerPrinter Validity VFS451
PCIE *1 + USB *1 daughter board Module
Page 23 USB*1 Page 23
Intel Ibex Peak M USB*1 Page 32
Azalia
USB conn x 3(For I/O)-Rear side, Power USB
PCI-E BUS 1071pins
25mm*27mm SATA0 BT Conn USB x 1 Page 24
SATA1
USB x1(Camara)
Page 20
10/100/1000 LAN WLAN Card Rico R5C835 Controller PCI BUS SATA3
Page 12,13,14,15,16,17
Intel Hanksville GbE Page 25
PHY PCIE*1 MDC V1.5 RJ11
Page 21 Page 22 ONFI Interface Page 28 Page 28
Audio CKT TPA6047A4RHBR
Braidwood
Page 23 IDT 92HD75 Page 26
AMP & Audio Jack Page 27
RJ45 CONN 1394 port Smart Card SD/MMC Slot
3 3
Page 21
Page 25 Page 25 Page 32
SATA ODD Connector
Page 22
NAND Flash Card
Page 23
1.8" SATA HDD Connector
LPC BUS Page 22
RTC CKT. LED
Page 29
Page 12 LED Board Docking CONN.
Page 28 (2) USB 1.channels
(1) Display Port Channels
SMSC KBC 1098 TPM1.2 SATA*1(Docking) Page 29 (1) Line In
Power OK CKT.
Page 33 page 30
SLB9635TT (1) Line Out
Page 32 (1) RJ45 (10/100/1000)
(1) VGA
(1) 2 LAN indicator LED's
4
Touch Pad CONN. (1) Power Button 4
Power On/Off CKT. Page 28 Int.KBD
(1) SATA
Page 28 Page 28
TrackPoint CONN.
Page 28 Security Classification Compal Secret Data Compal Electronics, Inc.
2008/09/15 2010/12/31 Title
DC/DC Interface CKT. 8 MB
Issued Date Deciphered Date
Block Diagram
Page 34
SPI ROM Page 31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5251P 0.9
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 05, 2010 Sheet 2 of 47
A B C D E
A
( O MEANS ON X MEANS OFF )
Voltage Rails Symbol Note :
+RTCVCC +B +5VALW +3VM +1.5V +5VS
+3VL +3VALW +1.05VM +0.75V +3VS
+1.5VS : means Digital Ground
power
plane +VCCP
+CPU_CORE
+1.05VS : means Analog Ground
+1.8VS
@ : means just reserve , no build
CONN@ : means ME part.
State SV@ : means just build on SV Sku. LV Sku no build.
LV@ : means just build on LV Sku. SV Sku no build.
L Layout Notes
01/04 update
S0
O O O O O O
: Question Area Mark.(Wait check)
S1
O O O O O O
S3
O O O O O X
Install below 45 level BOM structure for ver. 0.1
S5 S4/AC
O O O O X X 45@ : means just put it in the BOM of 45 level.
S5 S4/ Battery only
O O X X X X
S5 S4/AC & Battery
O X X X X X
1
don't exist
Install below 43 level BOM structure for ver. 0.1 1
DEBUG@ : means just build when PCIE port 80 CARD function enable. Remove before MP
SMBUS Control Table
THERMAL
SOURCE BATT XDP SODIMM CLK CHIP MINI CARD DOCK NIC SENSOR G-SENSOR
SMB_EC_CK1
SMB_EC_DA1
SMSC1098
V X X X X X X X X
SMBCLK
SMBDATA
Calpella X V V V V V X X V
SML0CLK
SML0DATA
Calpella X X X X X X V X X
SML1CLK
SML1DATA
Calpella X X X X X X X V V
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/09/15 Deciphered Date 2010/12/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-5251P 0.9
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 05, 2010 Sheet 3 of 47
A
1 2 3 4 5
Layout rule 10mil width trace
length < 0.5", spacing 20mil
U1B
20_0402_1% 1 R2 2 H_COM P3 AD71 COMP3 C LK_CPU_BCLK
BCLK AK7 CLK_CPU_BCLK 15
Misc
20_0402_1% 1 R5 2 H_COM P2 AC70 AK8 CLK_CPU_BCLK#
COMP2 BCLK# CLK_CPU_BCLK# 15
49.9_0402_1% 1 R7 2 H_COM P1 AD69 K71 CLK_CPU_XDP
COMP1 BCLK_ITP
Clocks
J70 CLK_CPU_XDP#
49.9_0402_1% 1 R9 H_COM P0 BCLK_ITP#
2 AE66 COMP0 CLK_EXP
07/09 update for INTEL S3 leakage issue.
PEG_CLK L21 CLK_EXP 13
J21 CLK_EXP#
PEG_CLK# CLK_EXP# 13 +1.5V
P AD T48 TP_SKTOCC# M71 PROC_DETECT R 1093
DPLL_REF_SSCLK Y2 C LK_DP 13
A W4 2 1 A
DPLL_REF_SSCLK# CLK_DP# 13
H _CATERR# N61 CATERR# 1K_0402_5%
SM_DRAMRST# 1 6 DRAMRST# 9,10
Thermal
BJ12 SM_DRAMRST#
SM_DRAMRST#
15 H_ PECI 1 R 14 2 H_PECI_ISO N19 PECI
Q52A
0_0201_5% BV33 SM_RCOMP0 2 R 1092 1 2N7002DWH 2N SOT363-6
2
SM_RCOMP[0] SM_RCOMP1
SM_RCOMP[1] BP39 P CH_ DDR_RST 15
to power; PU to VCCP at power side also BV40 SM_RCOMP2 @ 100K_0402_5%
SM_RCOMP[2]
DDR3
Misc
40 H _PROCHOT# 1 R 15 2 H_ PROCHOT#_D N67 PROCHOT#
C6 1 2 .1U_0402_16V7K
0_0201_5% AV66 PM_EXTTS#0 T49 P AD
PM_EXT_TS#[0] PM_EXTTS#1 1
PM_EXT_TS#[1] AV64 2 PM_EXTTS#1_R 9 ,10
0_0201_5% R 16 from DDR
07/17 update 08/28 update
15 H_THERMTRIP# 1 R 17 2 H_THERMTRIP#_R N17 THERMTRIP#
0_0201_5%
U71 XDP_PRDY#
PRDY# XDP _PREQ#
PREQ# U69
H _CPURST# 1 R 18 2 H_ CPURST#_R N70 T67 X DP_TCK
0_0201_5% RESET_OBS# TCK XDP_TMS
TMS N65
Power Management
1 R 19 2 H_P M_SYNC_R M17 P69 XDP_TRST#
14 H_ PM_SYNC PM_SYNC TRST#
0_0201_5%
T69 XDP_TDI
TDI
TDO T71
P71
X DP_TDO
X DP_TDI_M
CPU XDP Connector
TDI_M
JTAG & MBP
H_CP UP W RGD 1 R21 2 SYS_AGENT_P WROK AM7 T70 XDP _PREQ# JP4
0_0201_5% VCCPWRGOOD_1 TDO_M XDP_PRDY# 1 GND0 GND1 2
W71 XDP _DBRESET# 3 4
DBR# OBSFN_A0 OBSFN_C0 CFG8 5
15 H_CP UP W RGD 1 R 22 2 V CC PWRGOOD_0 Y67 VCCPWRGOOD_0
XDP_BPM#0 R23 1 2 0_0201_5% 5 OBSFN_A1 OBSFN_C1 6 CFG9 5
0_0201_5% @ R24 1 2 0_0201_5% 7 8
5 CFG 12 GND2 GND3
J69 XDP_BPM#0 XDP_BPM#1 R25 1 2 0_0201_5% 9 10
B BPM#[0] OBSDATA_A0 OBSDATA_C0 CFG0 5 B
14 PM_DRAM_PWRGD 1 R 26 2 V DDP W RGOOD_R AM5 SM_DRAMPWROK BPM#[1] J67 XDP_BPM#1
5 CFG 13
@ R27 1 2 0_0201_5% 11 OBSDATA_A1 OBSDATA_C1 12 CFG1 5
0_0201_5% J62 XDP_BPM#2 XDP_BPM#2 R28 1 2 0_0201_5% 13 14
from power BPM#[2] XDP_BPM#3 @R29 0_0201_5% GND4 GND5
BPM#[3] K65 5 CFG 14 1 2 15 OBSDATA_A2 OBSDATA_C2 16 CFG2 5
32 VTTPWRGOOD H15 K62 XDP_BPM#4 XDP_BPM#3 R30 1 2 0_0201_5% 17 18
VTTPWRGOOD BPM#[4] OBSDATA_A3 OBSDATA_C3 CFG3 5
J64 XDP_BPM#5 @R31 1 2 0_0201_5% 19 20
BPM#[5] 5 CFG 15 GND6 GND7 +3VS
0_0201_5% K69 XDP_BPM#6 21 22
BPM#[6] 5 CF G17 OBSFN_B0 OBSFN_D0 CFG 10 5
H_PWRGD_XDP 1 R 32 2 H _PWRGD_XDP_R Y70 M69 XDP_BPM#7 ESD request to add 23 24
TAPPWRGOOD BPM#[7] 5 CF G16 OBSFN_B1 OBSFN_D1 CFG 11 5
25 GND8 GND9 26
15 BUF_PLT_RST# 1 2R33 PLT_RST#_R G3 RSTIN#
XDP_BPM#4 0_0201_5% 1 2 R43 XDP_BPM#4_R 27 OBSDATA_B0 OBSDATA_D0 28 CFG4 5
2
XDP_BPM#5 0_0201_5% 1 2 R48 XDP_BPM#5_R 29 30
OBSDATA_B1 OBSDATA_D1 CFG5 5
1.5K_0402_1% 31 32 R34
GND10 GND11
1
+VCCP XDP_BPM#6 0_0201_5% 1 2 R40 XDP_BPM#6_R 33 34 1K_0201_5%
OBSDATA_B2 OBSDATA_D2 CFG6 5
XDP_BPM#7 0_0201_5% 1 2 R41 XDP_BPM#7_R 35 36
OBSDATA_B3 OBSDATA_D3 CFG7 5
R35 INTEL_AUBURNDALE_1288 1 R36 1K_0201_5% 37 38
1
H_CP UP W RGD 1 GND12 GND13
750_0402_1% 2 H_CP UP W RGD_R 39 PWRGOOD/HOOK0 ITPCLK/HOOK4 40 CLK_CPU_XDP
C1 PM_PWRBTN#_R 41 42 CLK_CPU_XDP# + VCCP
14 PM_PWRBTN#_R
2
0.1U_0402_16V4Z HOOK1 ITPCLK#/HOOK5 1K_0201_5%
43 VCC_OBS_AB VCC_OBS_CD 44
@ 2 H_PWRGD_XDP 1 XDP_RST#_R R38 H _CPURST#
2 45 HOOK2 RESET#/HOOK6 46 1 2
R37 0_0201_5% 47 48 XDP_DB RESET#_R 1 2 XDP _DBRESET#
HOOK3 DBR#/HOOK7 XDP_DBRESET# 12,14
49