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5 4 3 2 1



REVISIONS
REV DESCRIPTION DATE APPROVED
A1 FIRST RELEASE 06/07/04



D D




Topology Page 1.
Page 2.
Topology, Index
Reset Map
Page 3. Clock Distribution
Page 4. Power Delivery Map
Page 5. K7 - 1
Page 6. K7 - 2
K7 Page 7. Power VCCP
Page 5,6 Page 8. 741-1 Host & AGP
Page 9. 741-2 DDR
Page 10. 741-3 MuTIOL Link
Page 11. 741-4 Power
Host Bus
Page 12. 963-1 PCI/IDE/MuTIOL 1G
Page 13. 963-2 LPC/MII/CPU/GPIO
Page 14. 963-3 USB
Page 15. 963-4 Power
C

AGP BUS DDR SDRAM DIMM1 Page 16. CLK Generator
C

AGP SLOT
Page 18 Page 17. DDR Clock Buff
SiS741 DIMM2 Page 18. AGP
Page 8,9,10,11 Page 20,22
Page 19. VGA Connector
Page 20. DIMM1 & DIMM2
PCI Slot 1 Page 21. Blank
MuTIOL 1G Page 22. DDR Termination
Page 23. PCI 1&2
LAN PHY
PCI Slot 2 Page 24. PCI 3
Page 34,26
Page 25. IDE
PCI Slot 3 Page 26. USB, LAN Port
Page 23,24
Page 27. ITE8705
AC'97 Page 28. Keyboard Mouse
Audio Codec Page 29. COM/PRT Port
IDE 1
SiS963 Page 32,33
Page 30. BIOS/FLOPPY
Page 31. FAN
PS/2 Page 32. AC97 CODEC
IDE 2 Keyboard Page 12,13,14,15
B
Page 25 /Mouse Page 28
Page 33. AC97 I/O B


Back Panel Front Panel Page 34. LAN PHY
LPC Bus USB 0 USB 4 Page 35. Power BTN/RTC Batt
USB 5 Page 36. SB3V/SB1.8V/AUX_IVDD
USB 1 Page 26 Page 37. DDR2.5V/DDRVTT
Page 38. ATX Power
FAN 1 USB 2 Page 39. IVDD & AUX_IVDD
FAN CONTROL
FAN 2 Page 31
VOLTAGE MONITOR USB 3 Page 40. Change List
Page 26

LPC Super I/O TEMPERATURE MONITOR
ISA Bus Page 27
ISA ROM 30
Page




IR PARALLEL SERIAL FLOPPY
Page 27 Page 29 Page 29 Page 30
A A




FOXCONN PCEG
Title
Topology, Index
Size Document Number Rev
C 741M01C A

Date: Monday, June 07, 2004 Sheet 1 of 40
5 4 3 2 1
5 4 3 2 1



VCCP VCCP K7
VRD10/VRM9.X
VRMPWRGD
D D
CPUPWRGD




&
PWOK


NBPWRGD
ATX
Power SiS741
PSON_

C C
AGP 8X SLOT



SiS963
SBPWRGD PCI Slot 1
PCI Slot 2
PCI Slot 3


PCIRST_

Front Panel
PSON_

IDE CONN 1
B RSTSW_ SIORST_ B
IDE CONN 2
PWRBTN_
PWRBTN_




SIORST_ SIORST_

Super IO Media
Interface



A A


FOXCONN PCEG
Title
Reset Map
Size Document Number Rev
C 741M01C A

Date: Monday, June 07, 2004 Sheet 2 of 40
5 4 3 2 1




14.318MHz

CPU

CPUCLK0 100/133/200 MHz
D D



100/133/200 MHz
CPUCLK1


66 MHz AGP 8x




DDR CLOCK BUFFER
AGPCLK1

133 MHz
SiS741




DIMM 1-2
ZCLK0
66 MHz
FWDSDCLK0 DDRCLK
AGPCLK0
CLOCK GENERATOR




33 MHz
96XPCLK
133 MHz
ZCLK1

C
48 MHz C


UCLK48M
12 MHz
TXCLK
REFCLK
RXCLK LAN PHY

33 MHz
PCI Slot 1-3
SiS963
PCICLK1-3




AUDIO_CLK
32.768KHz
AC'97
24.576MHz/NC

48 MHz
B SIO48M Super I/O B




A A




FOXCONN PCEG
Title
Clock Distribution
Size Document Number Rev
C 741M01C A

Date: Monday, June 07, 2004 Sheet 3 of 40
5 4 3 2 1
5 4 3 2 1




ATX SPS
5 3 + -
V 5 . 1 1
S V 3 2 2
B V V V


D Socket A 462 D


+5V
> VRD 10 VCCP
> VCCP
1.1V~1.85V 41.4A
SIS963L


SIS741
SB1.8V
> VCC3
96mA
VCC1.8V
488mA
VCC3
>
VCC3
>
VCC3:
3.3V
VCC1.8V
1.8V
SB3V
> SB3V
275mA
SB1.8V
27mA
145mA 290mA VCC1.8V
>
SB3V
> AUX_IVDD
> VCCP
>
Linear
Power Regulator SB3V VDDQ: RTCVDD VCCP
AGP 3uA 15mA
26mA 1.5V
SB3V
> OR
SB5V
AMS1117
SB3V
> VCC2.5_MEM SB1.8V
3 VOLTS
BATTERY >
VCC_RTC
>
2.5V 1.8V
VCC3
Linear
Power Regulator
VCC1.8V
> 463mA 10mA
CLK_GEN
IVDD
1.9V
VCCP
1.5V
VCC3
> 3.3V
300mA
C
VCC3
Linear
Power Regulator
IVDD
> 2.614A 101mA
C



AUX_IVDD
1.9V
SB5V
> SUPER I/O
VCC3 VDDQ 1.5V
> 501.3mA
5V_SYS
> SB5V
SB3V
> 5V
Linear
Power Regulator SB3V
VCC3
>
PCI PER SLOT:
VCC5
> 3.3V 7.6A
VCC5
>
+12V
>
5V 5.0A
12V 0.5A
VCC3
>
OR
> FWH

-12V
> -12V 0.1A
3.3Vaux
SB3V
> 0.375A




LAN PHY
VCC5
> USB

SB3V
> 5V 3A

SB5V
> PS2 KB/MS

5V

B VDDQ 1.5V
> AGP +12V LM7805 VCC5A
>
B


+12V
> VCC5
>
OR
> AC' 97 AUDIO CODEC
VCC3
> VCC3
> A5V 70mA
3.3V 10mA
VCC5
>
SB3V
>
DDR 2 DIMMS:
VCC3 VCC2.5_MEM
>
Linear
Power Regulator
2.6V +/-100mv
6.00A




DDR VTT
VCC2.5_MEM
> RT9173 DDR_VTT_STR
> 1.3V
2A
A A




FOXCONN PCEG
Title
Power Delivery Map
Size Document Number Rev
C 741M01C A

Date: Monday, June 07, 2004 Sheet 4 of 40
5 4 3 2 1
8 7 6 5 4 3 2 1
Near socket-A
VCCP VCCP Push-pull compensation circuit

AMD K7 CPU 1 OF 2 COREFB R39 49.9 VCCP VCCP

COREFBJ R108 49.9
8 SDATA-[63:0] R105 R106
60.4 60.4 R120 R109
CN1A VCC3 +/-1% +/-1% 100 100
SDATA-0 AA35 AE1 A20MJ VCCP
SDATA0 A20M A20MJ 13
SDATA-1 W37 AG1 FERR Near socket-A
SDATA-2 SDATA1 FERR INITJ R111 +/-1% CLKOUTJ CLKOUT
W35 SDATA2 INIT AJ3 INITJ 13
SDATA-3 Y35 AL1 INTR R121 R99 301
SDATA3 INTR INTR 13
SDATA-4 U35 AJ1 IGNNEJ 680 510
SDATA4 IGNNE IGNNEJ 13
SDATA-5 U33 AN3 NMI CPUCK BC29 50V, X7R, +/-10% R119 R118
SDATA5 NMI NMI 13 CPUCLK 16




**
D D
SDATA-6 S37 AG3 CPURSTJ 680pF C0603 100 100
SDATA6 RESET CPURSTJ 8
SDATA-7 S33 AN5 SMIJ CPUCKJ BC30 50V, X7R, +/-10%
SDATA7 SMI SMIJ 13 R102 CPUCLKJ 16
SDATA-8 AA33 AC1 STPCLKJ 680pF C0603
SDATA8 STPCLK STPCLKJ 13
SDATA-9 AE37
SDATA-10 SDATA9 BC32 VCCP
AC33 SDATA10 PWROK AE3 PWRGD_CPU 10,38 Trace lengths of CLKOUT and
SDATA-11
SDATA-12
AC37
Y37
SDATA11
SDATA12
47pF * NP
301
FERRJ
FERRJ 13 VREF_SYS is set at 50%
-CLKOUT are between 2" and
SDATA-13 AA37 N1 3"
SDATA13 PICCLK PICCLKCPU 16 of VCC_CORE to CPU




C
SDATA-14 AC35 N3 R214
SDATA14 PICD0/BYPASSCLK APICD0 13
SDATA-15 S35 N5 FERR B Q11 100
SDATA15 PICD1/BYPASSCLK APICD1 13 MMBT3904
SDATA-16 Q37
SDATA-17 SDATA16 COREFBJ VCCP
Q35 SDATA17 COREFB- AG13




E
SDATA-18 N37 AG11 VREF_SYS
SDATA18 COREFB+ COREFB 7
SDATA-19 J33 SDATA19
SDATA-20
SDATA-21
G33
G37
SDATA20
SDATA21
CLKIN
CLKIN
AN17
AL17
CPUCK
CPUCKJ
* * BC99 * BC100 R215
ZN R131 40.2

SDATA-22
SDATA-23
E37
G35
SDATA22
SDATA23 RSTCLK AN19
* BC31
BC28
10nF VCCP
10nF 0.1uF
C0603
100 ZP R128 56

SDATA-24 Q33 AL19 10nF NP
SDATA-25 SDATA24 RSTCLK NP NP
N33 SDATA25
SDATA-26 L33 AL21 CLKOUT R138 124
SDATA-27 SDATA26 K7CLKOUT CLKOUTJ R0603 +/-1% VCCP
N35 SDATA27 K7CLKOUT AN21
SDATA-28 L37
SDATA-29 SDATA28 VCC3 VCC3 VCC3
J37
SDATA-30
SDATA-31
A37
E35
SDATA29
SDATA30 ANALOG AJ13 CPURSTJ
INTR
*
1
3
2 RN11
4 680 R134
SDATA-32 SDATA31 VREFMODE IGNNEJ
E31 SDATA32 SYSVREFMODE AA5 5 6 1K
SDATA-33 E29 W5 VREF_SYS A20MJ 7 8 NP
SDATA-34 SDATA33 VREF_SYS R218 VREFMODE
A27
SDATA-35
SDATA-36
A25
E21
SDATA34
SDATA35 ZN AC5
AE5
ZN
ZP
SMIJ
INITJ
*
1
3
2 RN10
4 680
R217
330