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A B C D E
SYSTEM DC/DC
LZ2 Block Diagram
TPS51120 36
Project code: 91.4K101.001 ZY LZ2
91.4J301.001 XR LX2 INPUTS OUTPUTS
PCB P/N : 07260-SB 5V_S5
DCBATOUT
Revision : SA 3D3V_S5
4 Mobile CPU SYSTEM DC/DC
4
CLK GEN. EMC2102 TPS51124 37
3
Penryn SV 35W 07
PCB 8-LAYER STACKUP INPUTS OUTPUTS
4, 5 TOP 1D05V_S0
DCBATOUT
1D5V_S3
HOST BUS 800/[email protected] GND
S
TPS51100 38
800/1066MHz
DDR3 socket Cantiga
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R.G.B CRT S DDR_VREF_S0
AGTL+ CPU I/F 18
15 PWR 1D5V_S3 (1.5A)
DDR Memory I/F
DDR_VREF_S3
INTEGRATED GRAHPICS LVDS S
LVDS, CRT I/F
12"W LCD
800/1066MHz
DDR3 socket 8,9,10,11,12,13,14
17 GND
33
3 BOTTOM
3
16 X4 DMI
C-Link0 1D5V_S3 1D5V_S0
400MHz
INT MIC
Codec CHARGER
AZALIA
ALC269 ICH9M Realtek BQ24740 39
(include AMP) SD/MMC/MS INPUTS OUTPUTS
25 6 PCIe ports USB RTS5158E
3 in 1
PCI/PCI BRIDGE Cardreader 28 CHG_PWR
SPR x2 ACPI 1.1 18V
28 DCBATOUT
4 SATA UP+5V
12 USB 5V 100mA
MIC In
CPU DC/DC
High Definition Audio PCIe
LAN ADP3208
35
2 HP Boardcom RJ45 2
LPC I/F 27
5906M 26 INPUTS OUTPUTS
Serial Peripheral I/F
DCBATOUT VCC_CORE
PCIe/ USB Mini Card
a/b/g/n 31
MODEM
RJ11 MDC Card
24
19,20,21,22,23 LPC BUS
SATA
SATA
Finger Print KBC
USB
New card PCI Express / USB
32
Winbond SPI I/F
LPC
DEBUG
31 WPC776 CONN. 24
29
BlueTooth
1 24
1
Power switch G-sensor Touch INT. BIOS Digitally signed by dd
SATA-HDD SATA-ODD Wistron Corporation
21F, 88, Sec.1,cn=dd, o=dd, ou=d
DN: Hsin Tai Wu Rd., Hsichih,
CAMERA Pad 34 KB 34 2M byte
31 24 24 30 34 Taipei Hsien 221, Taiwan, R.O.C.
17
Title
[email protected]
USB
BLOCK DIAGRAM c=US
3 Port Size Document Number Rev
LZ2 Date: 2009.12.04 SB 19:55:
A3
32
Date: Friday, April 11, 2008
+07'00'
Sheet 1 of 41
A B C D E
ICH9M Integrated Pull-up Cantiga chipset and ICH9M I/O controller
ICH9M Functional Strap Definitions Hub strapping configuration
ICH9 EDS 642879 Rev.1.5 and Pull-down Resistors Montevina Platform Design guide 22339 0.5
4 ICH9 EDS 642879 Rev.1.5 page 218 4
Signal Usage/When Sampled Comment Pin Name Strap Description Configuration
SIGNAL Resistor Type/Value
HDA_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 CL_CLK[1:0] PULL-UP 20K CFG[2:0] FSB Frequency 000 = FSB1067
PCIE Port Config1 bit1, pulled low.When TP3 not pulled low at rising edge Select 011 = FSB667
Rising Edge of PWROK of PWROK,sets bit1 of RPC.PC(Config Registers: CL_DATA[1:0] PULL-UP 20K 010 = FSB800
offset 224h). This signal has weak internal pull-down others = Reserved
CL_RST0# PULL-UP 20K
CFG[4:3] Reserved
HDA_SYNC PCIE config1 bit0, This signal has a weak internal pull-down. DPRSLPVR/GPIO16 PULL-DOWN 20K CFG8 CFG11
Rising Edge of PWROK. Sets bit0 of RPC.PC(Config Registers:Offset 224h) CFG[15:14]
ENERGY_DETECT PULL-UP 20K CFG[18:17]
GNT2#/ PCIE config2 bit2, This signal has a weak internal pull-up.
GPIO53 Rising Edge of PWROK. Sets bit2 of RPC.PC2(Config Registers:Offset 0224h) HDA_BIT_CLK PULL-DOWN 20K 0 = DMI x2
CFG5 DMI x2 Select
GPIO20 Reserved This signal has a weak internal pull-down. HDA_DOCK_EN#/GPIO33 PULL-UP 20K 1 = DMI x4 (Default)
Rising Edge of PWROK. Note:This signal should not be pulled high. CFG6 iTPM Host 0= The iTPM Host Interface is enabled(Note2)
HDA_RST# PULL-DOWN 20K Interface 1= The iTPM Host Interface is disalbed(default)
Tying this strap low configures DMI for SIcompatible
GNT1#/ ESI Strap(Server Only) operation. This signal has a weak internal pull-up. HDA_SDIN[3:0] PULL-DOWN 20K 0 = Transport Layer Security (TLS) cipher
GPIO51 Rising edge of PWROK NOTE: ESI compatible mode is for server latforms CFG7 Intel Management suite with no confidentiality
HDA_SDOUT PULL-DOWN 20K engine Crypto strap
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only. This signal should not be pulled low for 1 = TLS cipher suite with confidentiality (default)
desktop and mobile. HDA_SYNC PULL-DOWN 20K
0 = Reverse Lanes,15->0,14->1 ect..
GNT3#/ Top-Block Sampled low:Top-Block Swap mode(inverts A16 for GLAN_DOCK# The pull-up or pull-down active when configured for nativeCFG9 PCIE Graphics Lane 1= Normal operation(Default):Lane
GPIO55 Swap Override. all cycles targeting FWH BIOS space). GLAN_DOCK# functionality and determined by LAN controller Numbered in order
Rising Edge of PWROK. Note: Software will not be able to clear the GNT[3:0]#/GPIO[55,53,51] PULL-UP 20K
Top-Swap bit until the system is rebooted 0 = Enable (Note 3)
GPIO[20] PULL-DOWN 20K CFG10 PCIE Loopback enable 1= Disabled (default)
without GNT3# being pulled down.
GNT0#: GPIO[49] PULL-UP 20K 00 = Reserve
SPI_CS1#/ Boot BIOS Destination Controllable via Boot BIOS Destination bit CFG[13:12] XOR/ALL 10 = XOR mode Enabled
GPIO58 Selection 0:1. (Config Registers:Offset 3410h:bit 11:10). LDA[3:0]#/FHW[3:0]# PULL-UP 20K 01 = ALLZ mode Enabled (Note 3)
Rising Edge of PWROK. GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC. 11 = Disabled (default)
LAN_RXD[2:0] PULL-UP 20K
Integrated TPM Enable, Sample low: the Integrated TPM will be disabled. CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
3 SPI_MOSI Rising Edge of CLPWROK Sample high: the MCH TPM enable strap is sampled LDRQ[0] PULL-UP 20K 1 = Dynamic ODT Enabled (Default) 3
low and the TPM Disable bit is clear, the
Integrated TPM will be enable. LDRQ[1]/GPIO23 PULL-UP 20K 0 = Normal operation(Default):
CFG19 DMI Lane Reversal Lane Numbered in Order
PME# PULL-UP 20K
DMI Termination Voltage, The signal is required to be low for desktop 1 = Reverse Lanes
GPIO49 Rising Edge of PWROK. applications and required to be high for PWRBTN# PULL-UP 20K DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3)
mobile applications. DMI x2 mode[MCH -> ICH]:(3->0,2->1)
SATALED# PULL-UP 15K
PCI Express Lane SPI_CS1#/GPIO58/CLGPIO6 PULL-UP 20K Digital Display Port 0 = Only Digital Display Port
SATALED# Reversal. Rising Edge Signal has weak internal pull-up. Sets bit 27 (SDVO/DP/iHDMI) or PCIE is operational (Default)
of PWROK. of MPC.LR(Device 28:Function 0:Offset D8) SPI_MOSI PULL-DOWN 20K CFG20 Concurrent with PCIe 1 =Digital display Port and PCIe are
If sampled high, the system is strapped to the operting simulataneously via the PEG port
SPI_MISO PULL-UP 20K
SPKR No Reboot. "No Reboot" mode(ICH9 will disable the TCO Timer
Rising Edge of PWROK. system reboot feature). The status is readable SPKR PULL-DOWN 20K SDVO_CTRLDATA SDVO Present 0 = No SDVO Card Present (Default)
via the NO REBOOT bit. 1 = SDVO Card Present
TACH_[3:0] PULL-UP 20K
0 = LFP Disabled (Default)
TP3 TP[3] PULL-UP 20K Local Flat Panel
XOR Chain Entrance. This signal should not be pull low unless using L_DDC_DATA (LFP) Present 1= LFP Card Present; PCIE disabled
Rising Edge of PWROK. XOR Chain testing. USB[11:0][P,N] PULL-DOWN 15K
GPIO33/ NOTE:
HDA_DOCK Flash Descriptor Sampled low:the Flash Descriptor Security will be 1. All strap signals are sampled with respect to the leading edge of
_EN# Security Override Strap overridden. If high,the security measures will be the (G)MCH Power OK (PWROK) signal.
Rising Edge of PWROK in effect.This should only be enabled in manufacturing 2. iTPM can be disabled by a 'Soft-Strap' option in the
environments using an external pull-up resister. Flash-decriptor section of the Firmware. This 'Soft-Strap' is
activated only after enabling iTPM via CFG6.
Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time.
17,33,35,36,37,39,41 DCBATOUT DCBATOUT
2 7,19,29,34,36,39,40 3D3V_AUX_S5 3D3V_AUX_S5 2
SMBus 7,31,33,36,39 5V_AUX_S5 5V_AUX_S5
USB Table SMBC_G792
17,20,21,22,23,24,26,29,30,31,33,34,36,37,41 3D3V_S5 3D3V_S5
USB G7921 22,32,33,36,37,38,41 5V_S5 5V_S5
PCIE Routing Pair Device
10,12,13,15,16,33,37,38,41 1D5V_S3 1D5V_S3
LANE1 BroadCom LAN 0 JACK0
LANE2 MiniCard WLAN 1 NC 15,16,38 0D75V_S3 0D75V_S3
THER_SCL
LANE4 NewCard 2 JACK2 AV Panel
13,33,38 1D8V_S0 1D8V_S0
3 NC
KBC
4 BLUETOOTH 3,7,10,11,13,15,16,17,18,19,20,21,22,23,24,25,26,28,29,31,32,33,34,35,36,37,38,41 3D3V_S0 3D3V_S0
BAT_SCL
5 JACK1 BATTERY
7,13,17,18,22,23,24,25,33,34,35,41 5V_S0 5V_S0
6 Fringer Print
History: 7 Mini Card 4,5,6,8,10,11,12,13,19,22,33,37 1D05V_S0 1D05V_S0
8 CAMERA
3,5,13,19,20,22,31,33 1D5V_S0 1D5V_S0
LAB: 2008/01/02 9 NEW CARD SMB_CLK Mini Card
10 CARDREADER ICH9M
New Card
11 NC
1 1
SMBC_ICH CLK GEN
DDR II Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reference
Size Document Number Rev
C
LZ2 SB
Date: Wednesday, April 16, 2008 Sheet 2 of 41
A B C D E
4 4
3D3V_S0 3D3V_S0_CK505
1D5V_S0_CK505 1D5V_S0
L16
BLM11A121S-GP
1 2 BLM11A121S-GP
1 2 L14
1
1
1
1
1
1
1
1
C332 C329 C301 C321 C333 C336 C337 C327 3D3V_S0_CK505
1
1
1
1
1
1
1
1
C297 C316 C326 C300 C317 C302 C312 C298
SC1U10V3KX-3GP
SC10U10V5ZY-1GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
2
2
2
2
2
2
2
SC1U10V3KX-3GP
SC10U10V5ZY-1GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SC10U10V5ZY-1GP
2
2
2
2
2
2
2
2
1
X3