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V CC 3
VCC_CORE
R61 2 0 V CC _S ENSE
V CC _S ENSE 3 3 C16 8
H1 0
H1 2
H1 4
H1 6




K1 0
K1 2
K1 4
K1 6




M1 0
M1 2
M1 4
M1 6

N1 1
N1 3
N1 5
P1 0
P1 2
P1 4
P1 6

R1 1
R1 3
R1 5
T1 0
T1 2
T1 4
T1 6

U1 1
U1 3
U1 5
J1 1
J1 3
J1 5




L1 1
L1 3
L1 5




R45 7 U2 2
H8




K8




M8


N7
N9


P8


R7
R9

T8


U7
U9
J7
J9




L7
L9




HD#[0..63] U59A 4 1 .1U
3 HD# [0 ..63] HD#0 D1 0 V CC GND
D0 # 10K
HD#1 D1 1
D1 #
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC
CP UV CC




HD#2 C7 HA# [3 ..31] Z59 4 3 2
HD#3 C8 D2 # L3 HA# 3 HA# [3 ..31] 3 S RT RES #
HD#4 B9 D3 # A3 # K3 HA# 4 MA X82 1




Z59 3
HD#5 A9 D4 # A4 # J2 R44 3
D5 # A5 # HA# 5
HD#6 C1 0 L4 HA# 6
HD#7 B1 1 D6 # A6 # L1
D7 # A7 # HA# 7 R R45 8
HD# 8 C1 2 K5 HA# 8
HD#9 B1 3 D8 # A8 # K1 HA# 9 0
HD#10 A1 4 D9 # A9 # J1 HA#1 0
HD#11 B1 2 D10 # A10 # J3 HA#1 1
D11 # A11 # R46 1
HD#12 E1 2 K4 HA#1 2 S U SB #
HD#13 B1 6 D12 # A12 # G1 10 S U SB # V R _ON 1 6,3 3
D13 # A13 # HA#1 3 R
HD#14 A1 3 H1 HA#1 4 U2 3 V CC 3 V_ IO
HD#15 D1 3 D14 # A14 # E4 8 1
D15 # A15 # HA#1 5 GND EN
HD#16 D1 5 F1 HA#1 6 7 2
HD#17 D1 2 D16 # A16 # F4 HA#1 7 6 GND IN 3
HD#18 B1 4 D17 # A17 # F2 HA#1 8 5 GND OUT 4
HD#19 E1 4 D18 # A18 # E1 HA#1 9 GND ADJ C49 9 R44 6 C49 4 C49 3
HD#20 C1 3 D19 # A19 # C4 HA#2 0 MIC520 9BM
HD#21 A1 9 D20 # A20 # D3
D21 # A21 # HA#2 1 4.7U .1U 4.7U
HD#22 B1 7 D1 HA#2 2 10 K_1 %(0 805)
HD#23 A1 8 D22 # A22 # E2
D23 # A23 # HA#2 3
HD#24 C1 7 D5 HA#2 4 R44 5
HD#25 D1 7 D24 # A24 # D4 HA#2 5 VRIOS ET
HD#26 C1 8 D25 # A25 # C3 HA#2 6
HD#27 B1 9 D26 # A26 # C1 HA#2 7 1 0.2K (1%)
HD#28 D1 8 D27 # A27 # B3 HA#2 8
LOW POWER GTL+ DATA BUS




HD#29 B2 0 D28 # A28 # A3
D29 # A29 # HA#2 9
HD#30 A2 0 B2 HA#3 0 VCCT
LOW POWER GTL+ INTERFACE
HD#31 B2 1 D30 # A30 # C2
D31 # A31 # HA#3 1
HD#32 D1 9 A4 Z71 2 T P1 2
HD#33 C2 1 D32 # A32 # A5 Z71 3
D33 # A33 # TP 9
HD#34 E1 8 B4 Z71 4 T P1 0 IE RR # R59 5 1.5K
HD#35 C2 0 D34 # A34 # C5 Z71 5 IE RR #
HD#36 F1 9 D35 # A35 # T P1 1
HD#37 D2 0 D36 # V2 0
D37 # DE P0 # Z71 6 T P3 4 S LP # R60 2 1.5K
HD#38 D2 1 T2 1 Z71 7 1 0 S LP #
HD#39 H1 8 D38 # DE P1 # U2 1 TP 1
D39 # DE P2 # Z71 8 T P3 3
HD#40 F1 8 R2 1 Z71 9 T P3 1 P ICD 0 R62 7 R
D40 # DE P3 # P ICD 0
Mainboard 1 of 33




HD#41 J1 8 V1 8 Z72 0 TP 8
HD#42 F2 1 D41 # DE P4 # P2 1 Z72 1
D42 # DE P5 # TP 5
HD#43 E2 0 P2 0 Z72 2 T P3 0 P ICD 1 R62 4 R
HD#44 H1 9 D43 # DE P6 # U1 9 Z72 3 P ICD 1
HD#45 E2 1 D44 # DE P7 # T P3 2
HD#46 J2 0 D45 # C6
D46 # B RE Q0 # B RE Q0 # B RE Q0 # 3 FLUSH # R59 6 1.5K
HD#47 H2 1 T2 HRE Q# 0 FLUSH #
HD#48 L1 8 D47 # RE Q0 # V4 HRE Q# 1 HRE Q# 0 3
HD#49 G2 0 D48 # RE Q1 # V2 HRE Q# 2 HRE Q# 1 3 P R EQ# R62 8 1.5K
HD#50 P1 8 D49 # RE Q2 # W3 HRE Q# 3 HRE Q# 2 3 P R EQ#
HD#51 G2 1 D50 # RE Q3 # W5 HRE Q# 4 HRE Q# 3 3
HD#52 K1 8 D51 # RE Q4 # HRE Q# 4 3 T CK R60 1 1K
HD#53 K2 1 D52 # AB 2 T CK
D53 # A DS # A DS # A DS # 3
HD#54 M1 8 AB 1 Z72 4
HD#55 L2 1 D54 # A P0 # Y2 T P1 8 R60 5 1K
D55 # A P1 # Z72 5 T P1 5 T MS
HD#56 R1 9 A A2 1 Z72 6 T MS
D56 # B P2 # TP 4
HD#57 K1 9 Y2 1 Z72 7 TP 3
VCCT HD#58 T2 0 D57 # B P3 # W 21 Z72 8 T DI R60 3 15 0
D58 # BP M0 # T P3 5 T DI
HD#59 J2 1 W 19 Z72 9 TP 6
HD#60 L2 0 D59 # BP M1 # V2 1 Z73 0
HD#61 M1 9 D60 # BINIT # T4 TP 7 R60 6 15 0
R64 5 D61 # B NR # B NR # B NR # 3 T DO
HD#62 U1 8 E6 Z73 1 T DO
HD#63 R1 8 D62 # B E RR# AA 1 T P1 3
56 .2 _1% D63 # A E RR# Z73 2 T P1 4
AA 3 DB SY # T R ST # R4 6 1K
BPRI# U4 DB SY # T1 DR DY # DB SY # 3 T R ST #
CPURST # 3 B PR I# A6 B PR I# DR DY # V1 HIT # DR DY # 3
3 CPU RST # RS#0 U1 RE S ET # HIT # Y4 HITM# HIT # 3
3 RS# 0 RS#1 AA 2 RS0 # HITM# W2 Z73 3 HITM# 3
3 RS# 1 RS#2 W1 RS1 # RP # R1 T P1 6 V CC 3
RS2 # LOCK # HLOCK # HLOCK # 3
3 RS# 2 Z71 1 Y1 GTL+ Input VCCT
T P1 7 HT RDY # U2 RSP # W 20
T R DY # GTL+ Output P R DY # Z73 4 TP 2
3 HT R DY # DEFER# U3 R60 9
3 DEFER# DEFER# AD9 IE RR # R61 0 1K Z22 2
R4 2 110 _1% Z63 0 A A1 6 1.5V Open Drain Output IE RR # A C1 2 CP U_ FE RR # IE RR #
E DGEC T RLP FE RR # CP U_ FE RR #




B
1 6 GCL _A 20M# GCL_A20M# A D1 0 A B2 1 P ICD 0 Q6 4.7K
VCCT GCL_IGNNE# A C1 3 A 20M# P ICD 0 Y2 0 P ICD 0
1 6 GCL_ IGNNE # IGNNE # 1.5V Open Drain I/O P ICD 1 P ICD 1 P ICD 1
GCL_INIT # A A1 0 R4 7 1.5K E C FE RR #
1 6 GC L_INIT # GCL_INT R A B1 8 INIT # FE RR # 10
LIN T 0/INTR 1.5V CMOS Input 2N 390 4
1 6 GCL_ IN TR GCL_NMI A C1 9 A A1 1 T CK
1K 1 6 GC L_N MI P R EQ# A B2 0 LINT1 /N MI T CK A D1 3 T DI T CK R60 8 0(R)
R64 6 P R EQ# PWRGOOD V5 P R EQ# JTAG INTERFACE T DI A C1 5 T DO T DI
P W R GOOD Z75 9 A A1 2 P W R GOOD < -- 2 .5 C M O S In pu t T DO A D1 4 T MS T DO
R60 7 0 BS EL 1 A B1 5 BS EL 0 T MS A A1 4 T R ST # T MS CP U_ FE RR #
SLP# A B1 2 BS EL 1 T R ST # T R ST # CP U_ FE RR #
1 0 S LP # GCL_SMI# A B1 0 S LP #
1 6 GCL _SMI# SMI#
FLUSH # FLUSH# AC9 A A1 5 THE RMDP CP UP W R GD R7 1 0
GCL_ST PCLK# A C1 1 FLUSH # THERMAL INTERFACE THE RMDA A B1 6 THE RMDN THE RMDP 2 1 6 CP UP W R GD
1 6 GCL_S T PC LK # S T PCLK # THE RMDC THE RMDN 2
GCL _LO/HI# R2 D4
1 6 GCL _LO/HI# GHI# P W R OK C A P W R GOOD
HCLKCPU M3 3 ,1 0,3 0 P W R OK P W R GOOD
8 HCL KCPU PICCLK A A1 8 B CLK R7 0 1.5K
PICCLK F0 1J2 E(R) V_ IO
8 PICCLK




GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A1 2
A2 1



B1 0
B1 5
B1 8
C1 1
C1 5
C1 6
C1 9




E1 0
E1 1