Text preview for : Apple_Q41B_MLB_PB17_051-6694_RevC.rar part of apple Apple Q41B MLB PB17 051-6694 RevC apple Apple_Q41B_MLB_PB17_051-6694_RevC.rar



Back to : Apple_Q41B_MLB_PB17_051-6 | Home

8 7 6 5 4 3 2 1
CK ENG
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD APPD
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. REV ZONE ECN DESCRIPTION OF CHANGE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ. DATE DATE

C 358886PRODUCTION RELEASED 01/07/05 ?




D PAGE CONTENTS PAGE CONTENTS D

VIDEO CONNECTORS - INVERTER, DVI, S-VIDEO
SCHEM,MLB,PB17"
1 TITLE PAGE AND CONTENTS 22 DUAL-CHANNEL LVDS 01/07/2005
2 SYSTEM BLOCK DIAGRAM 23 LMU, LIGHT SENSOR, BOOTBANGER, SLEEP LED
SPIDEY - KBD,TPAD,HALL EFFECT,PWR BUTTON
3 POWER BLOCK DIAGRAM 24 MMM, BATTERY CURRENT SENSE

4 PCB NOTES AND HOLES
INTERNAL
25 CARDSLOT,CONNECTORS - LEFT USB/BLUETOOTH
HARD DRIVE,
DVD,
BOM OPTIONS STUFF NO STUFF
FAN CONTROLLER, MODEM, SOUND D3_HOT
5 MPC7450 MAXBUS INTERFACE 26 SERIAL DEBUG (JOLLY ROGER, PWR/NMI/RESET) D3_COLD
6 MPC7450 DATA 27 USB 2.0 GPU_SS
GPU_SWITCH
7 CPU PLL AND CONFIGURATION STRAPS 28 MARVELL GIGABIT ETHERNET PHY SERIAL_DEBUG
C 8 INTREPID MAXBUS AND BOOT STRAPS 29 FIREWIRE A/B PHY VCORE_OFFSET C
1_8V_MAXBUS
9 INTREPID MEMORY INTERFACE / BOOT ROM 30 FIREWIRE A/B CONNECTORS, PORT POWER LIMITER 1_5V_MAXBUS
10 DDR MEMORY MUXES 31 PMU (POWER MANAGEMENT UNIT) NEC_USB
11 200PIN DDR MEMORY SODIMM CONNECTORS 32 BATTERY CHARGER AND CONNECTOR INTREPID_USB
BBANG
12 INTREPID AGP 4X/PCI 33 12.8V SYSTEM POWER SUPPLY / PMU POWER SUPPLY NO_BBANG
13 INTREPID ENET/FW/UATA/EIDE INTERFACES 34 3.3V / 5V SYSTEM POWER SUPPLIES ATI_MEMIO_HI
ATI_MEMIO_LO
14 INTREPID GPIOS/SERIAL/USB INTERFACES/SSCG 35 CPU CORE VOLTAGE POWER SUPPLY
SSCG
15 INTREPID POWER RAILS 36 1.5V/ 1.8V / 2.5V SYSTEM POWER SUPPLIES NO_SSCG
5V_HD_LOGIC
B 16 INTREPID DECOUPLING 37 SIGNAL CONSTRAINTS (1 OF 3) - DIGITAL/CLK 3V_HD_LOGIC
B

17 CARDBUS CONTROLLER (PCI1510) 38 SIGNAL CONSTRAINTS (2 OF 3) - DIGITAL/DIFF EXT_TMDS
18 M11 AGP & CLOCKS 39 SIGNAL CONSTRAINTS (3 OF 3) - POWER NETS INT_TMDS
MMM
19 M11 LVDS/TMDS/VGA/GPIO & GPU VCORE 40 FUNCTIONAL TEST POINTS INT_CLK
20 SIL178 DUAL TMDS TRANSMITTER 41 REVISION HISTORY (1 OF 1) EXT_CLK

21 M11 ANALOG, POWER, GND 42-45 SCHEMATIC CREF AND NETLIST REPORTS
DIMENSIONS ARE IN MILLIMETERS

METRIC Apple Computer Inc.
XX


A X.XX
DRAFTER DESIGN CK NOTICE OF PROPRIETARY PROPERTY A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
X.XXX PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
ENG APPD MFG APPD
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
ANGLES II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
TABLE_5_HEAD QA APPD DESIGNER TITLE
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION DO NOT SCALE DRAWING

SCHEM,MLB,PB17"
TABLE_5_ITEM




051-6694 1 SCHEM,MLB,PB17 SCH1 RELEASE SCALE
TABLE_5_ITEM




820-1688 1 PCBF,MLB,PB17 PCB1 NONE

SIZE DRAWING NUMBER REV.
MATERIAL/FINISH
NOTED AS D 051-6694 C
THIRD ANGLE PROJECTION APPLICABLE SHT 1 OF 45

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
J18 J24 J22

Ethernet FW - A FW - B
Connector Connector Connector SLEEP
LED LMU
P.28 P.30 P.30 J25 J19
P.26
2 DATA PAIRS 2 DATA PAIRS Battery Power Supply SUTRO (PWR)
4 DATA PAIRS @ 200MHz Connector & Charger
U28
@ 400MHZ Connector
D U49 J11 P.32 P.32-36 P.32
D
FireWire OPTICAL DRIVE
Ethernet PHY J14
PHY P.29
Connector SMBUS U36
P.25 TUBA (SOUND)
P.28 Connector 3.3V LMU
G/MII J13 P.26 I2C
3.3V 1394 OHCI ULTRA ATA/100 U39
10/100/1000 3.3V Connector U48/J2/J4
P.24
8BIT TX 8BIT TX/RX
100MHZ P.25 EIDE
I2S I2C Fan
PMU
8BIT RX
125MHZ I2C Circuit P.31 J10
UIDE P.26 SERIAL CARDBUS
NOT USED Connector
J3 (SHARE WITH BLUETOOTH) 5V
ETHERNET FIREWIRE P.18
LEFT USB 10/100/1000 800 MB/S UATA 100 EIDE CARDSLOT P.15 P.14
P.14 P.14 P.14
I2S I2C J15
P.14 P.14 P.15 J5 Keyboard
P.25 USB 2.0

Serial Debug
TRACKPAD 33MHZ
C USB PORT A SCCA Connector Connector 16/32 BITS C
J12 P.15 Connector 3.3V/5V
P.15 KB LED
RIGHT USB P.26 U26
NOT USED USB PORT B LIGHT SENSOR
P.15 VIA/PMU P.24 TI PCI1510
BACKUP BATTERY
P.33 USB 2.0 U44 P.15 U17
USB PORT C
U52
CardBus
P.15 Controller
J3 (SHARE WITH LEFT USB)
BlueTooth NOT USED USB PORT D INTREPID BOOTROM
P.14
BOOT ROM
1M X 8 USB 2.0 P.18
P.25 P.15 P.10 CONTROLLER
USB PORT E PCI P.27
J9 P.15 32BITS PCI BUS
USB PORT F 33MHZ 32BITS
Modem Board P.13 33MHZ
Connector P.15 AGP BUS 3.3V
1.5V/3.3VU43
P.26 32BITS MEMORY MEMORY
MAXBUS 66MHZ CH. C
J21
P.9 4X AGP CH. A
B INTRPEID
I2C DDR MEMORY P.13 ATI M11 (INTERNAL MEM)
(INTERNAL MEM) AIRPOPT B
MAXBUS Connector
1.8V P.10 MEMORY MEMORY
167MHZ
32BIT ADDRESS MEMORY BUS
64MB CH. B CH. D
P.25
64BIT DATA 2.5V P.18-21 (INTERNAL MEM)(INTERNAL MEM)
167MHZ J8




EDID (I2C)
U42




COMPOSITE
U11/U12/U13/U14 64BITS
Inverter




S-VIDEO




(DDC TOO)
CPU PLL 2:1 DDR MUXES Connector
APOLLO




LVDS




TMDS

RGB
Config P.22
P.7 P.11
CPU
(MPC7457) J7 J17 J16
PMU
P.5-6 LCD Panel S-Video DVI-I
J20/J23 Connector Connector Connector
DDR SDRAM DIMM 0 P.22 P.22 P.22 SYSTEM BLOCK DIAGRAM
A NOTICE OF PROPRIETARY PROPERTY
A
DDR SDRAM DIMM 1 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

SO-DIMM Connector I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT

P.12 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.


APPLE COMPUTER INC.
D 051-6694 C
SCALE SHT OF
NONE 2 45
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

POWER SYSTEM ARCHITECTURE
+5V_MAIN
1V20_REF -

>~13.44V TURNS-ON
U21
PG 31
+
BACKLIGHT VCC MAP31 DDR I/O DCDC_EN
<~13.44V SHUTS-OFF
INVERTER MAIN 2.5V/1.5V MAP31 DDR CORE SLEEP




+PBUS
RUN/SS DDR POWER D
D AC DC/DC
ADAPTER INRUSH BUCK +2.5V_MAIN MAXBUS
LIMITER +24V_PBUS
VCC REGULATOR (MAX1715) SEQUENCING

IN PG 30
+PBUS (12.8V) PG 35 PGOOD 1_5V_2_5V_OK
(LTC1625)
PG 31 PG 32 SHUTDOWN: STOPPED
+5V_MAIN SLEEP: RUNNING +1.5V_MAIN
14V_PBUS AC: 12.8V
NO AC: BATTERY VOLTAGE RUN: RUNNING INTREPID CORE
1625 NOT RUNNING TURNS ON OUTPUT @ 2.4V AGP I/O +5V_MAIN
ON1/ON2
SHUTDOWN: RUNNING
SLEEP: RUNNING VCC SHDN
RUN: RUNNING
+5V_MAIN
DCDC_EN_L
AFTER PMU IS UP AND RUNNING DC/DC
RC AT 1M*0.047UF @ 24V DCDC_EN_L WILL PULL ON1/ON2
LOW IN SHUTDOWN (MAX1717)
+3V_PMU STARTS 2.0MSEC AFTER DCDC_EN_L BECOMES LOW
+5V_MAIN
+BATT PG 34
LDO +3V_PMU
RUN/SS - 5V EXT_VCC
+4_6V_BU TURNS ON AT >1V +5V_MAIN +PBUS (12.8V)
VCC SHUTDOWN: STOPPED
C PG 32
<100UA ALLOWED
INTERNAL ZENER CLAMP TO 6V
DC/DC SLEEP: STOPPED C
MAIN 3V/5V PGOOD 3V_5V_OK
(LTC1778) GPU_VCORE RUN: RUNNING
PG 20
DC/DC SHUTDOWN: STOPPED +1.2V/+1.0V
(LTC3707) HOLDS BOTH RUN/SS AT GND
DCDC_EN SLEEP: D3HOT/D3COLD CPU_VCORE
VCC PG 33 STBYMD
WHEN IT'S CONNECTED TO GND
TURNS CONTROL TO RUN/SS SLEEP
RUN: RUNNING (+1.4V/+1.5V)
+PBUS WHEN IT'S OPEN
D3_COLD
TURNS ON AS LOW AS 0.8V/TYP 1.5V
SHUTDOWN: STOPPED INTERNAL 1.2UA CURRENT SOURCE

SLEEP: RUNNING GPU_VCORE RUN/SS
1_5V_2_5V_OK WILL NOT PULL LOW UNTIL
RUN: RUNNING SEQUENCING
BACKUP 12.8V CHARGES BACKUP BATTERY
INTERNAL ZENER CLAMP TO 6V
<100UA ALLOWED +3.3V_MAIN
+5V_MAIN TURNS ON
HOWEVER, 5V SHOULD TURN ON ~2.23MS AFTER
1M & 0.1UF @14V, IT TAKES DCDC_EN_L OR PMU_POWERUP_L
BATTERY TURNS ON AT >1V
RUN/SS - 3V
~5.88MS TO START SWITCHER 1_5V_2_5V_OK
D3_HOT
BECOMES '1'; MUCH LESS THAN THE
RC CHARGING AT INT_VCC (5V)

DCDC_EN_L
D3_HOT
24V IS OUTPUT ONLY FROM
BACKUP BATTERY
RC AT 1M*0.1UF @ 24V
CHARGER INPUT STARTS ~4.25MSEC AFTER DCDC_EN_L BECOMES LOW
SHUT-DOWNRUN SLEEP RUN SHUT-DOWN
NO INRUSH PROTECTION
& BOOST OUTPUT WHEN ONLY BATTERY IS CONNECTED SLEEP
B PG 32 +24V_PBUS SLEEP_L_LS5 B
BACKUP BATTERY CIRCUIT CHARGES OFF +PBUS
DCDC_EN
AND PREVENTS +PBUS AND +24V_PBUS FROM DROPPING BELOW 6V DC/DC DCDC_EN_L
(UNTIL DRAINED)
(LTC3411)+1.8V_MAIN +5V_MAIN ~11MS
BATTERY PG 35 +5V_SLEEP
MAXBUS +3V_MAIN ~13.5MS
CHARGER SHUTDOWN: STOPPED BROADCOM
SLEEP: STOPPED +3V_SLEEP
(MAX1772) RUN: RUNNING 3V_5V_OK 2.4V - ??? MS

PG 31 +2_5V_MAIN 2.6 MS
+2_5V_SLEEP
+BATT +1_5V_MAIN 2.6 MS
NO INRUSH PROTECTION +1_5V_SLEEP
3S 3P PRISMATIC CELLS WHEN ONLY BATTERY IS CONNECTED 1_5V_2_5V_OK
(MAX1715 OUTPUT)

BATTERY VOLTAGE 1_5V_2_5V_OK
(AT LTC1778 RUN/SS)
POWER BLOCK DIAGRAM
A +PBUS ~???MS A
GPU_VCORE NOTICE OF PROPRIETARY PROPERTY
FEED-IN PATH (D3HOT)
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
GPU_VCORE
(D3COLD)
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

PG 31 +1_8V_MAIN
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT

1.9 MS III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.


APPLE COMPUTER INC.
D 051-6694 C
SCALE SHT OF
NONE 3 45
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

BOARD HOLES
CHASSIS MOUNTS
ASICS HEATSINK MOUNTS
I/O AREA
OMIT
INVERTER


PCB SPECS ZT10 OMIT
255R158 ZT5
146R126 1

D
1
OMIT
1 SH1
2 OG-503040 D
SHLD-SM
ZT2
255R158
CHGND5 3

1
OMIT BS1 CHGND2
STDOFF-217ODX150IDX35H-TH
ZT11
255R158 1

THICKNESS : 1.2 MM / 0.047 IN 1

OMIT
CHGND1
OMIT
1/2 OZ CU THICKNESS: 0.7 MILS ZT6
235R126
ZT83
146R126
1.0 OZ CU THICKNESS: 1.4 MILS 1
1

OMIT CHGND6
ZT16
235R126