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1 2 3 4 5 6 7 8
CPU CORE
VCC_CORE
+1.5V_RUN
X'TAL
14.31818MHz ZB3
MAX8736 VGA option
Page:31
+1.0V/+1.2V
Clock generator
Yonah/Yonah Celeron-M VGA Power
+1.2V +1.2V
MAX1993
A
(SC1470) ICS951413CGLFT INTEL Mobile_479 CPU Page:30
A
VCCP_+1.05V VCCP_+1.05V Page:5 SOCKET_M
Page:3, 4
(MAX1992) Page:32 VGA Memory
VGA_CORE
128MB/256MB
(Channel-B)
+1.8VSUS
HOST BUS 533/667MHZ Page:19
+1.8VSUS
+1.8V
+0.9V_VTER
(NCP5214) +0.9V_VTER RGB
Page:33 NB VGA CRT
PCI-E 16X
DDR-II SODIMM1 DDR-II 533/667MHz
ATi RC410ME ATI M52-P(M54-P) Page: 20
+3VPCU LVDS
+3VPCU/+5VPCU +3V_S5
Page: 10 533MHz/667MHz Page: 15, 16, LVDS
17, 18, 19 Page: 20
+3V_S5 +3VSUS 707-Pins FCBGA Package
+3V DDR-II SODIMM2 Page: 6 , 7, 8, 9
+3V/+5V Page: 10 UMA(option)
+5VPCU
B
+3VSUS/+5VSUS +5VSUS
B
15V +5V
MAX1999 15V MINI-Card
Page:34 Manufacturing Option 2X PCIE
2X PCIE Wireless LAN
Page: 22
SATA HDD MARVEL USB7
Page: 21 2X PCIE
BATTERY CHARGER SATA 88E8038
MAX8724 Page:35 64QFN-Pins Package BOTHHAND RJ45
BATTERY SB TRANSFORMER Page: 23
PATA HDD ATA 66/100 RTC Page: 23 NS0013
Power State Table Page: 21 Page: 23
Page: 11
ATi SB460
Power Control Power 549-Pins BGA Package
Name Signal State IDE-ODD PCI BUS 33MHZ
Page: 21 TI PCI7412 PCMCIA
VCC_CORE VRON S0 Azalia Cardbus controller SLOT
Page: 11, 12, 13, 14 USB 2.0 Page: 24
C VCCP_+1.05V MAINON S0 C
AD17
MIC-IN
+3VPCU N/A ALWAYS AUDIO CODEC REQ3# / GNT3#
+3V_S5 S5_ON S0-S5 Page: 26 REALTEK- ALC883 INTE#, INTH#, 5 IN1 CARD
+3VSUS SUSD S0-S3 X'TAL LPC 33MHZ
48-pins Package 32.768KHz INTG#(share) READER
+3V MAIND S0 Page: 24,25
LINE-IN Page: 26 Page: 25
+5VPCU N/A ALWAYS Page: 26
+5VSUS SUSD S0-S3 KBC
BIOS
+5V MAIND S0 NS PC97551 MINI-PCI
Audio AMP MODEM 176-Pins Package Page: 28
MAX9755 Wireless LAN
15V N/A S0 Page: 28
AD20
Page: 27 Page: 26
Bluetooth
REQ2# / GNT2#
+1.2V MAINON S0 USB
interface INTF#,
VGA_CORE VGA_MAINON S0 Page:22 INTG#(share)
Page: 22
USB6
+2.5V MAINON S0 SPEAKER RJ11 Touchpad Keyboard Audio DJ FAN
(Delay 1ms) SYSTEM
Page: 27 Page: 23 Page: 26 Page: 29 Page: 27 Page: 29 USB PORT*3
D D
+0.9V_VTER MAINON S0 Page: 22
+1.8V_S5 S5_ON S0-S5 USB0,2,4
+1.8VSUS SUSON S0-S3 PROJECT : ZB3
+1.8V MAIND S0
Quanta Computer Inc.
+1.5V_RUN MAINON S0 Size Document Number R ev
BLOCK DIAGRAM 1A
Date: Monday, April 03, 2006 Sheet 1 of 37
1 2 3 4 5 6 7 8
5 4 3 2 1
TABLE OF CONTENTS
POWER VOLTAGE ACTIVE SCOPE PAGE
Page 01 : BLOCK DIAGRAM POWER UP SEQUENCE
Page 02 : TABLE OF CONTENTS 15V 15V S0 33
Page 03 : Yanah CPU(HOST Bus)-1 +5V + 5V S0 33 +5VPCU
Page 04 : Yanah CPU(POWER/NC)-2 +3V +3.3V S0 33
RSMRST#
Page 05 : CLOCK GENERATOR +5VPCU + 5V ALWAYS 33
SYSTEM
D
Page 06 : RC410ME-MEMORY_AGTL+ I/F +3VPCU +3.3V ALWAYS 33 SUSB#, SUSC# D
Page 07 : RC410ME-PCIE LINK EXTERNAL VGA +5VSUS + 5V S0-S3 33
15V,+5V,+3V
Page 08 : RC410ME-LVDS OUT & CLKGEN +3VSUS +3.3V S0-S3 33
Page 09 : RC410ME-POWER +3V_S5 +3.3V S0-S5 33 HWPG_1.2V
Page 10 : DDR2 SO-DIMM X2 & TERMINA
Page 11 : SB460M-PCIE/PCI/CPU/LPC VCC_CORE VID[0..6] S0 31 HWPG_1.8V
CPU
Page 12 : SB460M ACPI/GPIO/USB/AC97 VCCP_+1.05V +1.05V S0 31
Page 13 : SB460M HDD/POWER/DECOUPLI +1.5V_RUN +1.5V S0 31 HWPG_VGA
Page 14 : SB460M STRAPS VCCP_+1.05V +1.05V S0 31 IMVP_PWRGD
Page 15 : M52-P_MAIN_PCIE (1 of 4) +1.8V +1.8V S0 33
NB_PWRGD
Page 16 : M52-P_MEM_GND (2 of 4) +1.8VSUS +1.8V S0-S3 33
Page 17 : M52-P_Power_LVDS(3 of 4) +1.2V +1.2V S0 32 EC_PWRGD
Page 18 : M52-P_Straps (4 of 4) +3V +3.3V S0 33
H_PWRGD
Page 19 : VGA RAM (64BIT DDR2) +1.2V_PCIE +1.2V S0 9
RC410ME NB
Page 20 : CRT & LVDS +1.2V_CORE +1.2V S0 9 PCIRST#
Page 21 : HDD & CDROM ,HOLES
C C
VDD18 +1.8V S0 9
H_RESET#
Page 22 : MINI PCI, USB Bluetooth PORT VDDA18 +1.8V S0 9
Page 23 : LAN PCI-E EE88038 NB_VDDR +3.3V S0 8
Page 24 : PCI7412-PCMCIA CONTROLLE
T1 T2 T3
AVDD_NB +3.3V S0 8
Page 25 : PCI7412-CARD READER AVDDQ +1.8V S0 8 T1>= 70 ms 1ms < T2 < 10ms
Page 26 : CODEC T/P MIC/LINE-IN/OUT-ALC883
1ms < T3 < 5ms
PLVDD +1.8V S0 8
Page 27 : AUDIO AMP&LINE OUT NB_LPVDD +1.8V S0 8
Page 28 : PC97551 & FLASH NB_LVDDR18A +1.8V S0 8
Page 29 : FAN,SWITCH,LED,KB
Page 30 : VGA CORE 1.0V/1.2V +3V +3.3V S0 33
Page 31 : CPU CORE-MAX8736ETL+ +1.8V +1.8V S0 33
Page 32 : +VCCP(1.05V)& 1.2V(NB PWR +3V_S5 +3.3V S0-S5 33
Page 33 : DDRII PWR_1.8VSUS-VTERM +1.8V_S5 +1.8V S0-S5 30
Page 34 : SYSTEM +5V& +3V MAX1999A VCCP_+1.05V +1.05V S0 31
B
Page 35 : BATTERY CHARGER +1.8VUSB_PHY +1.8V S0-S5 13 B
V5_REF + 5V S0 13
+1.8V_ATA +1.8V Reserve 13
SB460 SB
PLLVDD_ATA +1.8V Reserve 13
XTLVDD_ATA +1.8V Reserve 13
PCIE_PVDD +1.8V S0 11
PCIE_VDDR +1.8V S0 11
AVDD_USB +3VSUS S0-S3 12
+3.3V_AVDDC +3.3V S0-S3 12
VCCRTC +3.0V -- 11
VDDQ_3V +3.3V S0 13
VDD_1.8V +1.8V S0 13
SB_S5_3V +3.3V S0-S5 13
SB_S5_1.8V +1.8V S0-S5 13
AVDD_CK_1.8V +1.8V S0 13
A A
+1.8V +1.8V S0 33
DDR2
+1.8VSUS +1.8V S0-S3 10
+0.9V_VTER +0.9V S0 10
PROJECT : ZB3
Quanta Computer Inc.
Size Document Number R ev
BLOCK DIAGRAM 1A
Date: Monday, April 03, 2006 Sheet 2 of 37
5 4 3 2 1
5 4 3 2 1
H_A#[3..16] U34A
6 H_A#[3..16] T29 VCCP_+1.05V H_D#[0..63] H_D#[0..63]
H_A#3 J4 H1 U34B
A[3]# ADS# H_ADS# 6 6 H_D#[0..63] H_D#[0..63] 6
H_A#4 L4 E2 H_D#0 E22 AA23 H_D#32
A[4]# BNR# H_BNR# 6 D[0]# D[32]#
H_A#5 M3 G5 H_D#1 F24 AB24 H_D#33
A[5]# BPRI# H_BPRI# 6 D[1]# D[33]#
1
H_A#6 K5 H_D#2 E26 V24 H_D#34
H_A#7 A[6]# R132 H_D#3 D[2]# D[34]# H_D#35
M1 A[7]# DEFER# H5 H_DEFER# 6 H22 D[3]# D[35]# V26
ADDR GROUP 0
DATA GRP 0
H_A#8 200_4 H_D#4 H_D#36
DATA GRP 2
N2 A[8]# DRDY# F21 H_DRDY# 6 F23 D[4]# D[36]# W25
H_A#9 J1 E1 H_D#5 G25 U23 H_D#37
D A[9]# DBSY# H_DBSY# 6 D[5]# D[37]# D
CONTROL
H_A#10 N3 H_D#6 E25 U25 H_D#38
2
H_A#11 A[10]# H_D#7 D[6]# D[38]# H_D#39
P5 A[11]# BR0# F1 H_BR0# 6 E23 D[7]# D[39]# U22
H_A#12 P2 H_D#8 K24 AB25 H_D#40
H_A#13 A[12]# D[8]# D[40]#
L1 A[13]# IERR# D20 H _IERR# H_D#9 G24 D[9]# D[41]# W22 H_D#41
H_A#14 P4 B3 H_INIT# H_D#10 J24 Y23 H_D#42
A[14]# INIT# H_INIT# 11 D[10 D[42]#
H_A#15 P1 H_D#11 J23 AA26 H_D#43
A[15]# T37 D[11]# D[43]#
H_A#16 R1 H4 H_D#12 H26 Y26 H_D#44
A[16]# LOCK# H_LOCK# 6 D[12]# D[44]#
L2 H_RS#[2..0] 6 H_D#13 F26 Y22 H_D#45
6 H_ADSTB#0 ADSTB[0]# D[13]# D[45]#
6 H_REQ#[0..4] B1 H_RESET# H_D#14 K22 AC26 H_D#46
RESET# H_RESET# 6 D[14]# D[46]#
H_REQ#0 K3 F3 H_RS#0 H_D#15 H25 AA24 H_D#47
H_REQ#1 REQ[0]# RS[0]# H_RS#1 D[15]# D[47]#
H2 REQ[1]# RS[1]# F4 6 H_DSTBN#0 H23 DSTBN[0]# DSTBN[2]# W24 H_DSTBN#2 6
H_REQ#2 K2 G3 H_RS#2 G22 Y25
REQ[2]# RS[2]# 6 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 6
H_REQ#3 J3 G2 J26 V23
REQ[3]# TRDY# H_TRDY# 6 6 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 6
H_REQ#4 L5
H_A#[17..31] REQ[4]# T31 H_D#[0..63] H_D#[0..63]
6 H_A#[17..31] HIT# G6 H_HIT# 6 6 H_D#[0..63] H_D#[0..63] 6
H_A#17 Y2 E4 H_D#16 N22 AC22 H_D#48
A[17]# HITM# H_HITM# 6 D[16]# D[48]#
H_A#18 U5 H_D#17 K25 AC23 H_D#49
H_A#19 A[18]# ITP_BPM#0 H_D#18 D[17]# D[49]# H_D#50
R3 A[19]# BPM[0]# AD4 T3 P26 D[18]# D[50]# AB22
H_A#20 W6 AD3 ITP_BPM#1 H_D#19 R23 AA21 H_D#51
A[20]# BPM[1]# T90 D[19]# D[51]#
DATA GRP 1
XDP/ITP SIGNALS
H_A#21 ITP_BPM#2 Place voltage H_D#20 H_D#52
DATA GRP 3
U4 A[21]# BPM[2]# AD1 T89 L25 D[20]# D[52]# AB21
H_A#22 Y5 AC4 ITP_BPM#3 divider within H_D#21 L22 AC25 H_D#53
A[22]# BPM[3]# T7 0.5" of GTLREF D[21]# D[53]#
H_A#23 U2 AC2 ITP_BPM#4 H_D#22 L23 AD20 H_D#54
A[23]# PRDY# T91 pin D[22]# D[54]#
H_A#24 R4 AC1 XDP_BPM#5 H_D#23 M23 AE22 H_D#55
H_A#25 A[24]# PREQ# XDP_TCK H_D#24 D[23]# D[55]# H_D#56
T5 A[25]# TCK AC5 P25 D[24]# D[56]# AF23
H_A#26 T3 AA6 XDP_TDI H_D#25 P22 AD24 H_D#57
H_A#27 A[26]# TDI XDP_TDO VCCP_+1.05V H_D#26 D[25]# D[57]# H_D#58
W3 A[27]# TDO AB3 T18 P23 D[26]# D[58]# AE21
H_A#28 W5 AB5 XDP_TMS H_D#27 T24 AD21 H_D#59
H_A#29 A[28]# TMS XDP_TRST# H_D#28 D[27]# D[59]# H_D#60
Y4 A[29]# TRST# AB6 R24 D[28]# D[60]# AE25
H_A#30 W2 C20 XDP_DBRESET# H_D#29 L26 AF25 H_D#61
H_A#31 A[30]# DBR# H_D#30 D[29]# D[61]# H_D#62
Y1 A[31]# T25 D[30]# D[62]# AF22
6 H_ADSTB#1 V4 ADSTB[1]# PROCHOT D21 H_PROCHOT# H_D#31 N24 D[31]# D[63]# AF26 H_D#63
THERMDA A24 H_THERMDA 6 H_DSTBN#1 M24 DSTBN[1]# DSTBN[3]# AD23 H_DSTBN#3 6
THERM
H_A20M# A6 A25 H_THERMDC R105 N25 AE24
C 11 H_A20M# A20M# THERMDC 6 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 6 C
H _FERR# A5 1K/F_4 M26 AC20
11 H_FERR# FERR# 6 H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 6
H_IGNNE# C4 C7 H_THERMTRIP#
11 H_IGNNE# IGNNE# THERMTRIP#
R143 0_4 V_CPU_BTLREF AD26 R26 COMP0
H_STPCLK# GTLREF COMP[0] COMP1
11 H_STPCLK# D5 STPCLK#
MISC COMP[1] U26
C6 *1K/F_4 U1 COMP2
H CLK
11 H_INTR LINT0 COMP[2]
B4 A22 R504 1 2 TEST1 C26 V1 COMP3
11 H_NMI LINT1 BCLK[0] CLK_CPU_BCLK 5 TEST1 COMP[3]
H_SMI# A3 A21 R100
11 H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# 5
2K/F_4 R506 1 1K/F_4
2 TEST2 D25 E5 H_DPRSTP#
TP_RSVD#1 TEST2 DPRSTP#
T22 AA1 RSVD[01]# DPSLP# B5 H_DPSLP# 11
TP_RSVD#2 AA4 T22 TP_RSVD#12 Pop R694 for Yonah B0 & forward D24
T23 RSVD[02]# RSVD[12]# T25 DPWR# H_DPWR# 6
TP_RSVD#3 AB2 B22 D6
T15 RSVD[03]# 5 CPU_HBSEL0 BSEL[0] PWRGOOD H_PWRGD 11
TP_RSVD#4
RESERVED
T21 AA3 RSVD[04]# 5 CPU_HBSEL1 B23 BSEL[1] SLP# D7 H_CPUSLP# 12
2