Text preview for : HP_COMPAQ_V3500_-_WISTRON_TIBET_-_SC.rar part of HP HP COMPAQ V3500 - WISTRON TIBET - SC HP HP_COMPAQ V3500 HP_COMPAQ_V3500_-_WISTRON_TIBET_-_SC.rar



Back to : HP_COMPAQ_V3500_-_WISTRON | Home

5 4 3 2 1




Tibet Block Diagram SYSTEM DC/DC
MAX8734A


INPUTS OUTPUTS
DDRII
DDRII 667/800 Channel A
AMD CPU Slot 0
3D3V_S5
D NPT Processor DCBATOUT D
5V_S5
Rev. G DDRII
DDRII 667/800 Channel B
S1 package Slot 1
7,8
SYSTEM DC/DC
3,4,5,6
MAX8743

HyperTransport
INPUTS OUTPUTS
16X16
6.4GB/S
1D2V_HT_S0
DCBATOUT
HDCP 1D2V_CORE_S0
HDCP HDCP SVIDEO/COMP TVOUT
EEPROM 14

RGB CRT CRT MAXIM CHARGER
HDMI 14
MAX8725
PCI-E X 1
9,10,11,12,13
PCIE x 1/ USB2.0 EXPRESSCARD
Mini Card 29
INPUTS OUTPUTS
C
PCIE x 1 PCI-E X 1 C
802.11a/b/g27
LCD
nVIDIA Power DCBATOUT
BT+
18V 3.0A
LVDS Dual Channel
UP to 1920 X 120116 MCP67 Switch 5V 100mA
ACPI 2.0 RICOH R553829
RJ45 10/100/1000 PHY RGMII MAC
CONN 29 MARVELL CPU DC/DC
88E3018 28,29 MAX8760

1394 INPUTS OUTPUTS
RICOH
Conn 26 Bluetooth
R5C833 32
VCC_CORE_S0
PCI PCI
5 in 1 1* 1394 DCBATOUT 1.35V
5 in 1 card reader USB x 2 35A
Card reader
26 25,26
8xUSB 2.0 USB 2.0
USB x 1 24


AMOM ATA 133 PATA ODD
B RJ11 MODEM 24 B
PCB LAYER
CONN CX20548 HD AUDIO HD AUDIO
SATA SATA HDD
24
LINE OUT L1:SIGNAL 1
HD AUDIO
CODEC LPC I/F LPC Bus L2:GND
LINE OUT/SPDIF
CX20549-12Z 17,18,19,20,21,22
33
L3:SIGNAL 2

L4:SIGNAL 3
MIC IN
L5:VCC
INTERNAL MIC ARRAY KBC SPI
L6:SIGNAL 4
WINBOND
WPC8763
30
OP AMP
A
34 ANPEC APA2031 test
A
34


2CH SPEAKER Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Capacitive Comsumer Touch Int. Thermal FlashRom Taipei Hsien 221, Taiwan, R.O.C.
Button IR Pad KB & Fan 8Mb Title
32 33 32 32 G792 23 (1MB) 31
Block Diagram
DOCKING Size Document Number Rev
A3
1616 TIBET SA
Date: Tuesday, August 14, 2007 Sheet 1 of 44

5 4 3 2 1
5 4 3 2 1




3D3V_AUX_S5
3D3V_RTC_S5




SC1U25V5KX-1GP




SC1U25V5KX-1GP
D D




C688
1




1
1D2V_CORE_S0 1D2V_S0




C687
G67




2




2
1 2
GAP-CLOSE-PWR
G68
1 2
GAP-CLOSE-PWR
G84
1 2
GAP-CLOSE-PWR
G86
1 2 AD_JK
GAP-CLOSE-PWR
G85
1 2
GAP-CLOSE-PWR 5V_S0 1D2V_HT_S0 1D2V_S0
G87
1 2 3D3V_S0
GAP-CLOSE-PWR
G88
1 2
GAP-CLOSE-PWR DY DY
DY DY




C689




C690




C691




C692




C693



C694




C699



C700
SC1U6D3V3KX-2GP




SC1U6D3V3KX-2GP




SC1U6D3V3KX-2GP




SC1U6D3V3KX-2GP
G89




Do Not Stuff



Do Not Stuff




Do Not Stuff



Do Not Stuff
1



1
1 2 1 1 1 1 1 1
GAP-CLOSE-PWR
G90 2 2 2 2 2 2




2



2
1 2
C G91
GAP-CLOSE-PWR
C
1 2
GAP-CLOSE-PWR




B B
28,30 PHY_RESET#_KBC
3D3V_AUX_S5


U74
R575

R576 4 3 1 2

1 2 5 2 Do Not Stuff
Do Not Stuff 6 1
DY
DY Do Not Stuff


DY
28 RGMII_RESET#_PHY




A test
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title


Size Document Number Rev
A3
TIBET SA
Date: Tuesday, August 14, 2007 Sheet 2 of 44
5 4 3 2 1




D D




CPU1A

NB0HTTCLKOUT1
J5 CPUHTTCLKOUT1
Y4 CPUHTTCLKOUT1 9
9 NB0HTTCLKOUT1 NB0HTTCLKOUTJ1 L0_CLKIN_H1 L0_CLKOUT_H1 CPUHTTCLKOUTJ1
9 NB0HTTCLKOUTJ1 K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 CPUHTTCLKOUTJ1 9
R90 NB0HTTCLKOUT0
J3 CPUHTTCLKOUT0
Y1 CPUHTTCLKOUT0 9
1D2V_HT_S0 51R2J-2-GP 9 NB0HTTCLKOUT0 NB0HTTCLKOUTJ0 L0_CLKIN_H0 L0_CLKOUT_H0 CPUHTTCLKOUTJ0
9 NB0HTTCLKOUTJ0 J2 L0_CLKIN_L0 L0_CLKOUT_L0 W1 CPUHTTCLKOUTJ0 9

1 2 CPUHTTCTLIN1 P3 T5
CPUHTTCTLINJ1P4 L0_CTLIN_H1 L0_CTLOUT_H1
1 2 L0_CTLIN_L1 L0_CTLOUT_L1 R5
NB0HTTCTLOUTN1 CPUHTTCTLOUT0
R2 CPUHTTCTLOUT0 9
9 NB0HTTCTLOUT NB0HTTCTLOUTJ L0_CTLIN_H0 L0_CTLOUT_H0 CPUHTTCTLOUTJ0
9 NB0HTTCTLOUTJ P1 L0_CTLIN_L0 L0_CTLOUT_L0 R3 CPUHTTCTLOUTJ0 9
51R2J-2-GP
R92
C 9 NB0CADOUT[15..0]
NB0CADOUT15 N5
NB0CADOUTJ15 P5 L0_CADIN_H15 L0_CADOUT_H15
CPUCADOUT15
T4
CPUCADOUTJ15
T3
CPUCADOUT[15..0] 9
CPUCADOUTJ[15..0] 9
C
9 NB0CADOUTJ[15..0] NB0CADOUT14 M3 L0_CADIN_L15 L0_CADOUT_L15 CPUCADOUT14
L0_CADIN_H14 L0_CADOUT_H14 V5
NB0CADOUTJ14M4 CPUCADOUTJ14
U5
NB0CADOUT13 L5 L0_CADIN_L14 L0_CADOUT_L14 CPUCADOUT13
L0_CADIN_H13 L0_CADOUT_H13 V4
NB0CADOUTJ13M5 CPUCADOUTJ13
V3
NB0CADOUT12 K3 L0_CADIN_L13 L0_CADOUT_L13 CPUCADOUT12
L0_CADIN_H12 L0_CADOUT_H12 Y5
NB0CADOUTJ12 K4 CPUCADOUTJ12
W5
NB0CADOUT11 H3 L0_CADIN_L12 L0_CADOUT_L12 CPUCADOUT11
L0_CADIN_H11 L0_CADOUT_H11 AB5
NB0CADOUTJ11H4 CPUCADOUTJ11
AA5
NB0CADOUT10 G5 L0_CADIN_L11 L0_CADOUT_L11 CPUCADOUT10
L0_CADIN_H10 L0_CADOUT_H10 AB4
NB0CADOUTJ10H5 CPUCADOUTJ10
AB3
NB0CADOUT9 F3 L0_CADIN_L10 L0_CADOUT_L10 CPUCADOUT9
L0_CADIN_H9 L0_CADOUT_H9 AD5
NB0CADOUTJ9 F4 CPUCADOUTJ9
AC5
NB0CADOUT8 E5 L0_CADIN_L9 L0_CADOUT_L9 CPUCADOUT8
L0_CADIN_H8 L0_CADOUT_H8 AD4
NB0CADOUTJ8 F5 CPUCADOUTJ8
AD3
L0_CADIN_L8 L0_CADOUT_L8
HYPERTRANSPORT
NB0CADOUT7 N3 CPUCADOUT7
T1
NB0CADOUTJ7 L0_CADIN_H7 L0_CADOUT_H7 CPUCADOUTJ7
N2 L0_CADIN_L7 L0_CADOUT_L7 R1
NB0CADOUT6 L1 CPUCADOUT6
U2
NB0CADOUTJ6 L0_CADIN_H6 L0_CADOUT_H6 CPUCADOUTJ6
M1 L0_CADIN_L6 L0_CADOUT_L6 U3
NB0CADOUT5 L3 CPUCADOUT5
V1
NB0CADOUTJ5 L0_CADIN_H5 L0_CADOUT_H5 CPUCADOUTJ5
L2 L0_CADIN_L5 L0_CADOUT_L5 U1
NB0CADOUT4 J1 CPUCADOUT4
W2
NB0CADOUTJ4 L0_CADIN_H4 L0_CADOUT_H4 CPUCADOUTJ4
K1 L0_CADIN_L4 L0_CADOUT_L4 W3
NB0CADOUT3 G1 CPUCADOUT3
AA2
NB0CADOUTJ3 L0_CADIN_H3 L0_CADOUT_H3 CPUCADOUTJ3
H1 L0_CADIN_L3 L0_CADOUT_L3 AA3
NB0CADOUT2 G3 CPUCADOUT2
AB1
NB0CADOUTJ2 L0_CADIN_H2 L0_CADOUT_H2 CPUCADOUTJ2
G2 L0_CADIN_L2 L0_CADOUT_L2 AA1
NB0CADOUT1 E1 CPUCADOUT1
AC2
B NB0CADOUTJ1 F1
L0_CADIN_H1
L0_CADIN_L1
L0_CADOUT_H1
L0_CADOUT_L1
CPUCADOUTJ1
AC3 B
NB0CADOUT0 E3 CPUCADOUT0
AD1
NB0CADOUTJ0 L0_CADIN_H0 L0_CADOUT_H0 CPUCADOUTJ0
E2 L0_CADIN_L0 L0_CADOUT_L0 AC1




A test
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CPU(1/4) HT
Size Document Number Rev
A3
TIBET SA
Date: Tuesday, August 14, 2007 Sheet 3 of 44
5 4 3 2 1




D CPU1C D
MB0_CLK_H2 AF18 M_B_CLK_DDR2 7
7 M_B_DQ[63..0] MB0_CLK_L2 AF17 M_B_CLK_DDR2# 7
M_B_DQ63 AD11 A17 M_B_CLK_DDR1 7
M_B_DQ62 AF11 MB_DATA63 MB0_CLK_H1
MB_DATA62 MB0_CLK_L1 A18 M_B_CLK_DDR1# 7
M_B_DQ61 AF14
M_B_DQ60 AE14 MB_DATA61
MB_DATA60 MB0_CS_L3 Y26 M_B_CS3# 7,8
CPU1B M_B_DQ59 Y11 J24 M_B_CS2# 7,8
M_B_DQ58 AB11 MB_DATA59 MB0_CS_L2
MB_DATA58 MB0_CS_L1 W24 M_B_CS1# 7,8
Y16 M_A_CLK_DDR2 7 M_B_DQ57 AC12 U23 M_B_CS0# 7,8
MA0_CLK_H2 M_B_DQ56 AF13 MB_DATA57 MB0_CS_L0
7 M_A_DQ[63..0] MA0_CLK_L2 AA16 M_A_CLK_DDR2# 7 MB_DATA56
M_A_DQ63
AA12 E16 M_A_CLK_DDR1 7 M_B_DQ55 AF15 W23 M_B_ODT1 7,8
M_A_DQ62 MA_DATA63 MA0_CLK_H1 M_B_DQ54 AF16 MB_DATA55 MB0_ODT1
AB12 MA_DATA62 MA0_CLK_L1 F16 M_A_CLK_DDR1# 7 MB_DATA54 MB0_ODT0 W26 M_B_ODT0 7,8
M_A_DQ61
AA14 M_B_DQ53 AC18
M_A_DQ60 MA_DATA61 M_B_DQ52 AF19 MB_DATA53
AB14 MA_DATA60 MA0_CS_L3 V19 M_A_CS3# 7,8 MB_DATA52 MB_CAS_L V26 M_B_CAS# 7,8
M_A_DQ59
W11 J22 M_A_CS2# 7,8 M_B_DQ51 AD14 U22 M_B_WE# 7,8
M_A_DQ58Y12 MA_DATA59 MA0_CS_L2 M_B_DQ50 AC14 MB_DATA51 MB_WE_L
MA_DATA58 MA0_CS_L1 V22 M_A_CS1# 7,8 MB_DATA50 MB_RAS_L U24 M_B_RAS# 7,8
M_A_DQ57
AD13 T19 M_A_CS0# 7,8 M_B_DQ49 AE18
M_A_DQ56 MA_DATA57 MA0_CS_L0 M_B_DQ48 AD18 MB_DATA49
AB13 MA_DATA56 MB_DATA48 MB_BANK2 K26 M_B_BS#2 7,8
M_A_DQ55
AD15 V20 M_A_ODT1 7,8 M_B_DQ47 AD20 T26 M_B_BS#1 7,8
M_A_DQ54 MA_DATA55 MA0_ODT1 M_B_DQ46 AC20 MB_DATA47 MB_BANK1
AB15 MA_DATA54 MA0_ODT0 U19 M_A_ODT0 7,8 MB_DATA46 MB_BANK0 U26 M_B_BS#0 7,8
M_A_DQ53
AB17 M_B_DQ45 AF23
M_A_DQ52Y17 MA_DATA53 M_B_DQ44 AF24 MB_DATA45
MA_DATA52 MA_CAS_L U20 M_A_CAS# 7,8 MB_DATA44 MB_CKE1 H26 M_B_CKE1 7,8
M_A_DQ51Y14 U21 M_A_WE# 7,8 M_B_DQ43 AF20 J23 M_B_CKE0 7,8
M_A_DQ50 MA_DATA51 MA_WE_L M_B_DQ42 AE20 MB_DATA43 MB_CKE0
W14 MA_DATA50 MA_RAS_L T20 M_A_RAS# 7,8 MB_DATA42
M_A_DQ49
W16 M_B_DQ41 AD22 J25 M_B_A15
M_A_DQ48 MA_DATA49 M_B_DQ40 AC22 MB_DATA41 MEMORY
MB_ADD15 M_B_A14
AD17 MA_DATA48 MA_BANK2 K22 M_A_BS#2 7,8 MB_DATA40 MB_ADD14 J26 M_B_A[15..0] 7,8
M_A_DQ47Y18 R20 M_A_BS#1 7,8 M_B_DQ39 AE25 INTERFACE MB_ADD13 W25 M_B_A13
MA_DATA47 MA_BANK1 MB_DATA39
C M_A_DQ46
AD19
M_A_DQ45
AD21
MA_DATA46 MA_BANK0 T22 M_A_BS#0 7,8 M_B_DQ38 AD26
M_B_DQ37 AA25 MB_DATA38 MB_ADD12 L23
L25
M_B_A12
M_B_A11 C
M_A_DQ44 MA_DATA45 M_B_DQ36 AA26 MB_DATA37 MB_ADD11 M_B_A10
AB21 MA_DATA44 MA_CKE1 J20 M_A_CKE1 7,8 MB_DATA36 MB_ADD10 U25
M_A_DQ43
AB18 J21 M_A_CKE0 7,8 M_B_DQ35 AE24 L24 M_B_A9
M_A_DQ42 MA_DATA43 MA_CKE0 M_B_DQ34 AD24 MB_DATA35 MB_ADD9 M_B_A8
AA18 MA_DATA42 MB_DATA34 MB_ADD8 M26
M_A_DQ41
AA20 K19 M_A_A15 M_B_DQ33 AA23 L26 M_B_A7
M_A_DQ40Y20 MA_DATA41 MEMORY MA_ADD15 M_A_A14 M_B_DQ32 AA24 MB_DATA33 MB_ADD7 M_B_A6
MA_DATA40 MA_ADD14 K20 M_A_A[15..0] 7,8 MB_DATA32 MB_ADD6 N23
M_A_DQ39
AA22 INTERFACE MA_ADD13 V24 M_A_A13 M_B_DQ31 G24 N24 M_B_A5
M_A_DQ38Y22 MA_DATA39 M_A_A12 M_B_DQ30 G23 MB_DATA31 MB_ADD5 M_B_A4
MA_DATA38 MA_ADD12 K24 MB_DATA30 MB_ADD4 N25
M_A_DQ37
W21 L20 M_A_A11 M_B_DQ29 D26 N26 M_B_A3
M_A_DQ36 MA_DATA37 MA_ADD11 M_A_A10 M_B_DQ28 C26 MB_DATA29 MB_ADD3 M_B_A2
W22 MA_DATA36 MA_ADD10 R19 MB_DATA28 MB_ADD2 P24
M_A_DQ35
AA21 L19 M_A_A9 M_B_DQ27 G26 P26 M_B_A1
M_A_DQ34 MA_DATA35 MA_ADD9 M_A_A8 M_B_DQ26 G25 MB_DATA27 MB_ADD1 M_B_A0
AB22 MA_DATA34 MA_ADD8 L22 MB_DATA26 MB_ADD0 T24
M_A_DQ33
AB24 L21 M_A_A7 M_B_DQ25 E24
M_A_DQ32Y24 MA_DATA33 MA_ADD7 M_A_A6 M_B_DQ24 E23 MB_DATA25 M_B_DQS7
MA_DATA32 MA_ADD6 M19 MB_DATA24 MB_DQS_H7 AF12
M_A_DQ31H22 M20 M_A_A5 M_B_DQ23 C24 AE12 M_B_DQS#7 M_B_DQS[7..0] 7
M_A_DQ30 MA_DATA31 MA_ADD5 M_A_A4 M_B_DQ22 B24 MB_DATA23 MB_DQS_L7 M_B_DQS6
H20 MA_DATA30 MA_ADD4 M24 MB_DATA22 MB_DQS_H6 AE16
M_A_DQ29E22 M22 M_A_A3 M_B_DQ21 C20 AD16 M_B_DQS#6
M_A_DQ28E21 MA_DATA29 MA_ADD3 M_A_A2 M_B_DQ20 B20 MB_DATA21 MB_DQS_L6 M_B_DQS5
MA_DATA28 MA_ADD2 N22 MB_DATA20 MB_DQS_H5 AF21 M_B_DQS#[7..0] 7
M_A_DQ27J19 N21 M_A_A1 M_B_DQ19 C25 AF22 M_B_DQS#5
M_A_DQ26 MA_DATA27 MA_ADD1 M_A_A0 M_B_DQ18 D24 MB_DATA19 MB_DQS_L5 M_B_DQS4
H24 MA_DATA26 MA_ADD0 R21 MB_DATA18 MB_DQS_H4 AC25
M_A_DQ25F22 M_B_DQ17 A21 AC26 M_B_DQS#4
M_A_DQ24F20 MA_DATA25 M_A_DQS7 M_B_DQ16 D20 MB_DATA17 MB_DQS_L4 M_B_DQS3
MA_DATA24 MA_DQS_H7 W12