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INTEGRATED CIRCUITS DATA SHEET TDA9852 I2C-bus controlled BTSC stereo/SAP decoder and audio processor Preliminary specification Supersedes data of 1996 Feb 28 File under Integrated Circuits, IC02 1997 Mar 11 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor FEATURES · Quasi alignment-free application due to automatic adjustment of channel separation via I2C-bus · High integration level with automatically tuned integrated filters · Input level adjustment I2C-bus controlled · Alignment-free SAP processing · dbx noise reduction circuit · Power supply · I2C-bus transceiver. Stereo decoder · Stereo pilot PLL circuit with ceramic resonator, automatic adjustment procedure for stereo channel separation, two pilot thresholds selectable via I2C-bus. Audio processor · Selector for internal and external signals (line in) · Automatic volume level control (control range +6 to -15 dB) · Interface for external noise reduction circuits · Volume control (control range +16 to -71 dB) · Special loudness characteristic automatically controlled in combination with volume setting (control range 28 dB) · Audio signal zero crossing detection between any volume step switching · Mute control at audio signal zero crossing · Mute control via I2C-bus. ORDERING INFORMATION TYPE NUMBER TDA9852 TDA9852H PACKAGE NAME DESCRIPTION GENERAL DESCRIPTION TDA9852 The TDA9852 is a bipolar-integrated BTSC stereo decoder with hi-fi audio processor (I2C-bus controlled) for application in TV sets, VCRs and multimedia. VERSION SOT270-1 SDIP42 plastic shrink dual in-line package; 42 leads (600 mil) QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 Ч 10 Ч 1.75 mm SOT307-2 1997 Mar 11 2 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor LICENSE INFORMATION A license is required for the use of this product. For further information, please contact COMPANY THAT Corporation BRANCH Licensing Operations TDA9852 ADDRESS 734 Forest St. Marlborough, MA 01752 USA Tel.: (508) 229-2500 Fax: (508) 229-2590 405 Palm House, 1-20-2 Honmachi Shibuya-ku, Tokyo 151 Japan Tel.: (03) 3378-0915 Fax: (03) 3374-5191 Tokyo Office QUICK REFERENCE DATA SYMBOL VCC ICC VoR,L(rms) GLA cs THDL,R VI, O(rms) AVL GC LB S/N PARAMETER supply voltage supply current CONDITIONS MIN. 8.0 - 100% modulation L + R; fi = 300 Hz - -3.5 fL = 300 Hz; fR = 3 kHz fi = 1 kHz THD < 0.5% 25 - 2 -15 -71 fi = 40 Hz line out (mono); Vo = 0.5 V (RMS) CCIR noise weighting filter (peak value) DIN noise weighting filter (RMS value) S/N signal-to-noise ratio audio section; Vo = 2 V (RMS); gain = 0 dB CCIR noise weighting filter (peak value) DIN noise weighting filter (RMS value) - - 94 107 - - dB dBA - - 60 73 - - dB dBA - TYP. 8.5 75 250 500 - 35 0.2 - - - 17 MAX. 9.0 95 - - +4.0 - - - +6 +16 - UNIT V mA mV mV dB dB % V dB dB dB Vcomp(rms) input signal voltage (RMS value) input level adjustm