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File information:
File name:24c04.pdf
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Size:124 kB
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MD5 Checksum:abbed2dda8afa3ad802c7b04a85b0919
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Original Chassis:24C04N-MBR
Descr:4 KBIT SERIAL I²C BUS EEPROM WITH USER-DEFINED BLOCK WRITE PROTECTION
Group:Electronics > Components > Integrated circuits >
Uploaded:2004-03-09 16:09:21
User:plamensl
Multipart:No multipart

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Extracted files:1
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24c04.pdfST24C04, ST25C04 ST24W04, ST25W04 4 Kbit Serial I2C Bus EEPROM with User-Defined Block Write Protection NOT FOR NEW DESIGN 1 MILLION ERASE/WRITE CYCLES with 40 YEARS DATA RETENTION SINGLE SUPPLY VOLTAGE: 3V to 5.5V for ST24x04 versions 2.5V to 5.5V for ST25x04 versions HARDWARE WRITE CONTROL VERSIONS: ST24W04 and ST25W04 PROGRAMMABLE WRITE PROTECTION TWO WIRE SERIAL INTERFACE, FULLY I2C BUS COMPATIBLE BYTE and MULTIBYTE WRITE (up to 4 BYTES) PAGE WRITE (up to 8 BYTES) BYTE, RANDOM and SEQUENTIAL READ MODES SELF TIMED PROGRAMMING CYCLE AUTOMATIC ADDRESS INCREMENTING ENHANCED ESD/LATCH UP PERFORMANCES 8 1 PSDIP8 (B) 0.25mm Frame 8 1 SO8 (M) 150mil Width Figure 1. Logic Diagram DESCRIPTION This specification covers a range of 4 Kbits I2C bus EEPROM products, the ST24/25C04 and the ST24/25W04. In the text, products are referred to as ST24/25x04, where "x" is: "C" for Standard version and "W" for hardware Write Control version. Table 1. Signal Names PRE E1-E2 SDA SCL MODE WC VCC VS





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