datasheets 74ls112 free download

File name 74ls112.pdf

SN54/74LS112A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the DUAL JK NEGATIVE J and K inputs may be allowed to change when the clock pulse is HIGH and EDGE-TRIGGERED FLIP-FLOP the bistable will perform according to the truth table as long as minimum set-up and hold time are observed. Input data is transferred to the outputs on the LOW POWER SCHOTTKY negative-going edge of the clock pulse. LOGIC DIAGRAM (Each Flip-Flop) J SUFFIX CERAMIC CASE 620-09 16 1 Q Q 5(9) 6(7) N SUFFIX PLASTIC CLEAR (CD) SET (SD) CASE 648-08 16 15(14) 4(10) J K 1 3(11) 2(12) 1(13) CLOCK (CP) D SUFFIX SOIC