datasheets 74ls165 free download

File name 74ls165.pdf

SN54/74LS165 8-BIT PARALLEL-TO-SERIAL SHIFT REGISTER The SN54 / 74LS165 is an 8-bit parallel load or serial-in register with complementary outputs available from the last stage. Parallel inputing occurs asynchronously when the Parallel Load (PL) input is LOW. With PL HIGH, 8-BIT PARALLEL-TO-SERIAL serial shifting occurs on the rising edge of the clock; new data enters via the SHIFT REGISTER Serial Data (DS) input. The 2-input OR clock can be used to combine two independent clock sources, or one input can act as an active LOW clock LOW POWER SCHOTTKY enable. CONNECTION DIAGRAM DIP (TOP VIEW) VCC CP2 P3 P2 P1 P0 DS Q7 J SUFFIX 16 15 14 13 12 11 10 9 CERAMIC CASE 620-09 NOTE: 16 The Flatpak version 1 has the same pinouts (Connection Diagram) as the Dual In-Line Package. 1 2 3 4 5 6 7 8 N SUFFIX PL CP1 P4 P5 P6 P7 Q7 GND PLASTIC 16 CASE 648-08 1 PIN NAMES LOADING (Note a) HIGH LOW D SUFFIX CP1, CP2 Clock (LOW-to-HIGH Going Edge) Inputs 0.5 U.L. 0.25 U.L. SOIC DS Serial Data Input