|System_3000_Memory_Module.pdf||1. Memory Module
The memory module is the high speed system memory for the System 3000. It has on-
board 32 bit error detection and correction (EDAC), refresh logic, and partial write logic.
There are two interleaved arrays which can read, write, partial write, and refresh
independently. This is accomplished by interleaving on address bit 2 so that even and odd
four byte addresses go to opposite arrays. Because read operations return 8 bytes of data,
they require both arrays to work together. Each array contains four 39 bit wide banks.
The 39 bits include 32 bits of data and 7 check bits. Depopulated options of the module
are possible by stuffing one, two, or all four of the banks in each array. This yields an 8,
16, or 32 megabyte memory module.
The memory chips used are 1 megabit dynamic rams (1 Mb DRAMs). When 4
megabit DRAMs become available, they may be used in the module with only jumper
changes. The stuffing options will then be 32, 64, or 128 megabytes per module. The