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File name:74ls114.pdf
[preview 74ls114]
Size:47 kB
Extension:pdf
MD5:7f7cadaeb8839b82bbe768ed7b85a987
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Model:74ls114 🔎
Original:74ls114 🔎
Descr: . Electronic Components Datasheets Various datasheets 74ls114.pdf
Group:Electronics > Other >
Uploaded:29-06-2020
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74ls114.pdfSN54/74LS114A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS114A offers common clock and common clear inputs and individual J, K, and set inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be DUAL JK NEGATIVE accepted. The logic level of the J and K inputs may be allowed to change when EDGE-TRIGGERED FLIP-FLOP the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum set-up times are observed. Input data is transferred LOW POWER SCHOTTKY to the outputs on the negative-going edge of the clock pulse. LOGIC DIAGRAM (Each Flip-Flop) J SUFFIX

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