datasheets 74ls114 free download

File name 74ls114.pdf

SN54/74LS114A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS114A offers common clock and common clear inputs and individual J, K, and set inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be DUAL JK NEGATIVE accepted. The logic level of the J and K inputs may be allowed to change when EDGE-TRIGGERED FLIP-FLOP the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum set-up times are observed. Input data is transferred LOW POWER SCHOTTKY to the outputs on the negative-going edge of the clock pulse. LOGIC DIAGRAM (Each Flip-Flop) J SUFFIX CERAMIC CASE 632-08 14 Q Q 1 5(9) 6(8) CLEAR (CD) 4(10) N SUFFIX TO SET (SD) PLASTIC OTHER K CASE 646-06 FLIP-FLOP 14 J 2(12) 3(11) 1 13 CLOCK (CP) D SUFFIX SOIC