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Design & Evaluation of a Metrology Class, Delta-Sigma Analogue to Digital Converter for the LHC project at CERN. Allan Belcher1, John Pett2 & John Pickering3 1 Signal Conversion Ltd, Swansea, UK 2SL Group, CERN, Geneva, Switzerland 3 Metron Designs Ltd, Norwich, UK 1 Introduction The new LHC (Large Hadron Collider) particle accelerator, currently under construction at CERN, Geneva, will employ some 1700 converters powering cryogenic magnets to steer twin beams around the 27km ring. The critical positioning of the beams is dynamically controlled by adjusting the magnet current from near zero to some 13kAmps to track a pre-determined current profile to within a few parts per million (ppm). The control is performed in a digital loop requiring A-D conversion capable of sub ppm performance at real independent data rates up to the kHz region. Since no commercial product was available to meet this requirement, especially in the anticipated working environment, one of us (John Pett) designed and developed an a-d converter using Delta-Sigma technology. When prototypes became available, CERN sought independent verification of its performance, by asking the other two of us, as "industry experts" to perform rigorous evaluation of its operation and key parameters. This paper outlines the CERN requirement as it relates to the A-D and describes at a functional level its operational characteristics and shows how simulation can verify its time domain characteristics. DC and Dynamic testing methods are described, along with the very difficult measurement source requirements. Finally an outline of the results is presented revealing that this converter technology, more often associated with digital audio, is quite capable of meeting very stringent metrology requirements. 2 Basic A-D Delta-Sigma Design The ADC employed in the digital regulation loops for LHC is described in [1]. The choice of Delta-Sigma as the conversion technology was, as far as was known at that time, the first time it had been utilised for very high performance DC & LF metrology application. Such applications had previously turned exclusively to DVM-like methods but in this case would not achieve the necessary resolution-bandwidth product to be useable in the LHC's proposed magnet current digital control loops. The basic structure chosen is shown in Fig. 1. After a number of prototype 1 MHz realisations were made, based on an CLK initial optimisation of parameters buffer 3 integrators comparator obtained via simulation, a third order input LOGIC inte