Philips 4014 free download

File name 4014.pdf

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: · The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC · The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4014B MSI 8-bit static shift register Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification 8-bit static shift register DESCRIPTION The HEF4014B is a fully synchronous edge-triggered 8-bit static shift register with eight synchronous parallel inputs (P0 to P7), a synchronous serial data input (DS), a synchronous parallel enable input (PE), a LOW to HIGH edge-triggered clock input (CP) and buffered parallel outputs from the last three stages (O5 to O7). HEF4014B MSI Operation is synchronous and the device is edge-triggered on the LOW to HIGH transition of CP. Each register stage is of a D-type master-slave flip-flop. When PE is HIGH, data is loaded into the register from P0 to P7 on the LOW to HIGH transition of CP. When PE is LOW, data is shifted to the first position from DS, and all the data in the register is shifted one position to the right on the LOW to HIGH transition of CP. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times Fig.1 Functional diagram. HEF4014BP(N): HEF4014BD(F): HEF4014BT(D): 16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America FAMILY DATA, IDD LIMITS category MSI Fig.2 Pinning diagram. See Family Specifications January 1995 2 Philips Semiconductors Product specification 8-bit static shift register HEF4014B MSI January 1995 3 Fig.3 Logic diagram. Philips Semiconductors Product specification 8-bit static shift register PINNING PE P0 to P7 DS CP parallel enable input parallel data inputs serial data input clock input (LOW to HIGH edge-triggered) HEF4014B MSI O5 to O7 buffered parallel outputs from the last three stages FUNCTION TABLES Serial operation INPUTS n 1 2 3 6 7 8 CP DS D1 D2 D3 X X X X PE L L L L L L X O5 X X X D1 D2 D3 OUTPUTS O6 X X X X D1 D2 no change O7 X X X X X D1 Notes 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial = positive-going transition = negative-going transition Dn = either HIGH or LOW n = number of clock pulse transitions n 1 CP Parallel operation INPUTS DS X X PE H X O5 P5 OUTPUTS O6 P6 no change O7 P7 AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (µW) 900 fi + (foCL) Ч VDD2 4 300 fi + (foCL) Ч VDD2 12 000 fi + (foCL) Ч VDD2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load cap. (pF) (foCL) = sum of outputs VDD = supply voltage (V) January 1995 4 Philips Semiconductors Product specification 8-bit static shift register AC CHARACTERISTICS VSS = 0 V; Tamb = 25