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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: · The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications · The IC06 74HC/HCT/HCU/HCMOS Logic Package Information · The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC4049 Hex inverting high-to-low level shifter Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Hex inverting high-to-low level shifter FEATURES · Output capability: standard · ICC category: SSI GENERAL DESCRIPTION The 74HC4049 is a high-speed Si-gate CMOS device and is pin compatible with the "4049" of the "4000B" series. It is specified in compliance with JEDEC standard no. 7A. The 74HC4049 provides six inverting buffers with a modified input protection structure, which has no diode connected to VCC. Input voltages of up to 15 V may therefore be used. 74HC4049 This feature enables the inverting buffers to be used as logic level translators, which will convert high level logic to low level logic, while operating from a low voltage power supply. For example 15 V logic ("4000B series") can be converted down to 2 V logic. The actual input switch level remains related to the VCC and is the same as mentioned in the family characteristics. At the same time each part can be used as a simple inverter without level translation. APPLICATIONS · Converting 15 V logic ("4000B" series) down to 2 V logic. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/tPLH CI CPD Note 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD Ч VCC2 Ч fi + (CL Ч VCC2 Ч fo) where: fi = input frequency in MHz fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in V (CL Ч VCC2 Ч fo) = sum of outputs ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". PARAMETER propagation delay nA to nY input capacitance power dissipation capacitance per buffer note 1 CONDITIONS HC CL = 15 pF; VCC = 5 V 8 3.5 14 ns pF pF UNIT December 1990 2 Philips Semiconductors Product specification Hex inverting high-to-low level shifter PIN DESCRIPTION PIN NO. 1 2, 4, 6, 10, 12, 15 3, 5, 7, 9, 11, 14 8 13, 16 VCC 1Y to 6Y 1A to 6A GND n.c. SYMBOL data outputs data inputs ground (0 V) not connected NAME AND FUNCTION positive supply voltage 74HC4049 Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December 1990 3 Philips Semiconductors Product specification Hex inverting high-to-low level shifter 74HC4049 Fig.5 Fig.4 Functional diagram. Input protection for HC4049. Single sided thick oxide field effect metal gate transistor as input protection. Fig.6 Logic diagram (one level shifter). FUNCTION TABLE INPUT nA L H Notes 1. H = HIGH voltage level L = LOW voltage level OUTPUT nY H L December 1990 4 Philips Semiconductors Product specification Hex inverting high-to-low level shifter RATINGS Limiting values in accordance with the Absolute Maximu