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File information:
File name:74ls73.pdf
[preview 74ls73]
Size:53 kB
Extension:pdf
MD5:8135e2f1f85cd321a1248ddcd2ac4552
Mfg:datasheets
Model:74ls73 🔎
Original:74ls73 🔎
Descr: . Electronic Components Datasheets Various datasheets 74ls73.pdf
Group:Electronics > Other >
Uploaded:07-08-2020
User:Anonymous
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74ls73.pdfSN54/74LS73A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54LS / 74LS73A offers individual J, K, clear, and clock inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may DUAL JK NEGATIVE be allowed to change when the clock pulse is HIGH and the bistable will per- EDGE-TRIGGERED FLIP-FLOP form according to the truth table as long as minimum set-up times are ob- served. Input data is transferred to the outputs on the negative-going edge of LOW POWER SCHOTTKY the clock pulse. LOGIC DIAGRAM (Each Flip-Flop) J SUFFIX CE

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