datasheets 74ls107 free download

File name 74ls107.pdf

SN54/74LS107A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS107A is a Dual JK Flip-Flop with individual J, K, Direct Clear and Clock Pulse inputs. Output changes are initiated by the HIGH-to-LOW transition of the clock. A LOW signal on CD input overrides the DUAL JK NEGATIVE other inputs and makes the Q output LOW. EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS107A is the same as the SN54 / 74LS73A but has corner power pins. LOW POWER SCHOTTKY CONNECTION DIAGRAM DIP (TOP VIEW) J SUFFIX VCC CD1 CP1 K2 CD2 CP2 J2 CERAMIC CASE 632-08 14 13 12 11 10 9 8 14 1 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. N SUFFIX PLASTIC 1 2 3 4 5 6 7 14 CASE 646-06 J1 Q1 Q1 K1 Q2 Q2 GND 1 D SUFFIX LOGIC SYMBOL SOIC 1 2 14 1 CASE 751A-02 1 J Q 3 8 J Q 5