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Download VIA Cyrix III docs - Microprocessor, CPU, PIC schematics and info
| File information: | |
| File name: | cyr3_board.pdf [preview Cyrix III] |
| Size: | 58 kB |
| Extension: | |
| MD5: | 193a506b0a6cffbdd07f34f0bd0ac563 |
| Mfg: | VIA |
| Model: | Cyrix III 🔎 |
| Original: | |
| Descr: | Application Note 127 Cyrix III CPU MotherBoard Design Considerations |
| Group: | Electronics > Components > Integrated circuits > Processor > |
| Uploaded: | 28-04-2005 |
| User: | raymondtau |
| Multipart: | No multipart |
| Information about the files in archive: | ||
| Decompress result: | OK | |
| Extracted files: | 1 | |
| File name | Text | |
| cyr3_board.pdf | Application Note 127 Cyrix III CPU MotherBoard Design Considerations Cyrix Processors REVISION HISTORY Date 5/20/99 4/5/99 Version 1.0 0.54 Revision Added Diagrams Page 5, Table 1, Pin AK30 Description. Changed description. Page 5, Table 1, Moved third column and changed heading. Other minor editing on pages 7, 8, 9,and 13 . Typo Page 5, AK30 pin BSEL1 changed to 1 = 133 MHz, 0 =100 MHz Changed MXs processor name to Cyrix III. Corrected typos. Added paragraphs to pages 4, 7, 8 and 9 Renamed document to include the word "Considerations" Renamed document to better reflect the content. Repaired Table 1-4. BSEL0 and BSEL1 columns were reversed. Changed BSEL66# to BSEL0, Changed BSEL133# to BSEL1. BSEL1 now requires pull-down 10K resistor instead of 200 ohm pull-up resistor. Pins now listed in Table 1-2. Bus speed signals redefined in Table 1-4. Initial Version C:\documentation\joshua\appnotes\cIII_board.fm 4/2/99 3/22/99 3/15/99 3/12/99 3/11/99 2/26/99 2/26/99 0.53 0.52 0.51 0.5 0.4 0. | |
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