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Download SST SST49LF020 docs - Memory, computer memory, flash memory, ram, eeprom, eprom schematics and info
| File information: | |
| File name: | SST49LF020.pdf |
| Size: | 1538 kB |
| Extension: | |
| MD5: | fbf62c09305336323438fd72c52c431f |
| Mfg: | SST |
| Model: | SST49LF020 🔎 |
| Original: | Datasheet 🔎 |
| Descr: | 2 Megabit LPC Flash |
| Group: | Electronics > Components > Integrated circuits > Memory > |
| Uploaded: | 18-05-2005 |
| User: | dupator |
| Multipart: | No multipart |
| Information about the files in archive: | ||
| Decompress result: | OK | |
| Extracted files: | 1 | |
| File name | Text | |
| SST49LF020.pdf | 2 Megabit LPC Flash SST49LF020 SST49LF0202 Mb LPC Flash Advance Information FEATURES: · Standard LPC Interface Conforms to Intel LPC Interface Specification 1.0 · Organized as 256K x8 · Flexible Erase Capability Uniform 4 KByte sectors Uniform 16 KByte overlay blocks 16 KBytes Top boot block protection Chip-Erase for PP Mode · Single 3.0-3.6V Read and Write Operations · Superior Reliability Endurance: 100,000 Cycles (typical) Greater than 100 years Data Retention · Low Power Consumption Active Read Current: 10 mA (typical) Standby Current: 10 µA (typical) · Fast Sector-Erase/Byte-Program Operation Sector-Erase Time: 18 ms (typical) Block-Erase Time: 18 ms (typical) Chip-Erase Time: 70 ms (typical) Byte-Program Time: 14 µs (typical) Chip Rewrite Time: 4 seconds (typical) Single-pulse Program or Erase Internal timing generation · Two Operational Modes Low Pin Count (LPC) Interface mode for in-system operation Parallel Programming (PP) Mode for fast p | |
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