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Now downloading free:SST SST49LF020

SST SST49LF020 free download

Memory, computer memory, flash memory, ram, eeprom, eprom schematics and info

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File name:SST49LF020.pdf
Size:1538 kB
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Mfg:SST
Model:SST49LF020 🔎
Original:Datasheet 🔎
Descr:2 Megabit LPC Flash
Group:Electronics > Components > Integrated circuits > Memory
Uploaded:18-05-2005
User:dupator
Multipart:No multipart

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File name SST49LF020.pdf

2 Megabit LPC Flash SST49LF020 SST49LF0202 Mb LPC Flash Advance Information FEATURES: · Standard LPC Interface ­ Conforms to Intel LPC Interface Specification 1.0 · Organized as 256K x8 · Flexible Erase Capability ­ Uniform 4 KByte sectors ­ Uniform 16 KByte overlay blocks ­ 16 KBytes Top boot block protection ­ Chip-Erase for PP Mode · Single 3.0-3.6V Read and Write Operations · Superior Reliability ­ Endurance: 100,000 Cycles (typical) ­ Greater than 100 years Data Retention · Low Power Consumption ­ Active Read Current: 10 mA (typical) ­ Standby Current: 10 µA (typical) · Fast Sector-Erase/Byte-Program Operation ­ Sector-Erase Time: 18 ms (typical) ­ Block-Erase Time: 18 ms (typical) ­ Chip-Erase Time: 70 ms (typical) ­ Byte-Program Time: 14 µs (typical) ­ Chip Rewrite Time: 4 seconds (typical) ­ Single-pulse Program or Erase ­ Internal timing generation · Two Operational Modes ­ Low Pin Count (LPC) Interface mode for in-system operation ­ Parallel Programming (PP) Mode for fast production programming · LPC Interface Mode ­ 5-signal communication interface supporting byte Read and Write ­ 33 MHz clock frequency operation ­ WP# and TBL# pins provide hardware write protect for entire chip and/or top boot block ­ Standard SDP Command Set ­ Data# Polling and Toggle Bit for End-of-Write detection ­ 5 GPI pins for system design flexibility · Parallel Programming (PP) Mode ­ 11 pin multiplexed address and 8 pin data I/O interface ­ Supports fast In-System or PROM programming for manufacturing · CMOS I/O Compatibility · Packages Available ­ 32-lead PLCC ­ 32-lead TSOP (8mm x 14mm) PRODUCT DESCRIPTION The SST49LF020 flash memory device is designed to interface with the LPC bus for PC and Internet Applicance applications. It provides protection for the storage and update of code and data in addition to adding system design flexibility through five General Purpose Inputs (GPI). The SST49LF020 is in compliance with Intel Low Pin Count (LPC) Interface Specification 1.0. Two interface modes are supported: LPC Mode for In-System programming and Parallel Programming (PP) Mode for fast factory programming. The SST49LF020 flash memory device is manufactured with SST's proprietary, high performance SuperFlash Technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST49LF020 device significantly improves performance and reliability, while lowering power consumption. The SST49LF020 device writes (Program or Erase) with a single 3.0-3.6V power supply. It uses less energy during Erase and Program than alternative flash memory technologies. The total energy consumed is a function of the applied voltage, current and time of application. Since for any give voltage range, the SuperFlash technology uses ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 526 1 less current to program and has a shorter erase time, the total energy consumed during any Erase

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