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SGS TDA8133 free download

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File name:TDA8133.pdf
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Mfg:SGS
Model:TDA8133 🔎
Original:Datasheet 🔎
Descr:5.1V +8V REGULATOR WITH DISABLE AND RESET
Group:Electronics > Components > Integrated circuits
Uploaded:19-05-2005
User:dupator
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File name TDA8133.pdf

TDA8133 5.1V +8V REGULATOR WITH DISABLE AND RESET . . . . . . . . ADVANCE DATA OUTPUT CURRENTS UP TO 0.75A FIXED PRECISION OUTPUT 1 VOLTAGE 5.1V ± 2% FIXED PRECISION OUTPUT 2 VOLTAGE 8V ± 2% OUTPUT 1 WITH RESET FACILITY OUTPUT 2 WITH DISABLE BY TTL INPUT SHORT CIRCUIT PROTECTION AT BOTH OUTPUTS THERMAL PROTECTION LOW DROP OUTPUT VOLTAGE DESCRIPTION The TDA8133 is a monolithic dual positive voltage regulator designed to provide fixed precision output voltages of 5.1V and 8V at currents up to 0.75A. An internal reset circuit generates a reset pulse when the output 1 decrease below the regulated voltage value. Output 2 can be disabled by TTL input. Short circuit and thermal protections are included in all the versions. PIN CONNECTIONS 9 8 7 6 5 4 3 2 1 Tab. connected to Pin 5 SIP9 (Plastic Package) ORDER CODE : TDA8133 OUTPUT 1 OUTPUT 2 N.C. RESET GROUND DISABLE DEL. CAP. INPUT 2 INPUT 1 8133-01.EPS March 1994 This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/5 TDA8133 BLOCK DIAGRAM IN 1 1 IN 2 2 REFERENCE OUT 1 9 OUT 1 6 PROTECTION RESET 3 RESET DELAY CAPACITOR DISABLE 4 DISABLE OUT 2 8 OUT 2 ABSOLUTE MAXIMUM RATINGS Symbol VIN VDIS VRST IO1, 2 Pt Tstg Tj DC Input Voltage Pin 1 Disable Input Voltage Output Voltage at Pin 6 Output Currents Power Dissipation Storage Temperature Junction Temperature Parameter Value 20 20 20 Internally Limited -65 to +150 0 to +150 o o Unit V V V C C THERMAL DATA Symbol Rth (j-c) Rth (j-a) Tj Parameter Maximum Thermal Resistance Junction-case Maximum Thermal Resistance Junction-ambient Maximum Recommended Junction Temperature Value 8 60 130 Unit o o C/W o C 2/5 8133-02.TBL C/W 8133-01.TBL Internally Limited 8133-02.EPS 5 TDA8133 TDA8133 ELECTRICAL CHRACTERISTICS (VIN1 = 7V, VIN2 = 10V, Tj = 25oC, unless otherwise specified) Symbol VO1 VO2 VO1 VO2 VIO1,2 VO1,2LI Output Voltage Output Voltage Output Voltage Output Voltage Dropout Voltage Line Regulation Parameter Test Conditions IO1 = 10mA IO2 = 10mA 7V < VIN1 < 14V 10V < VIN2 < 14V 5mA < IO1,2 < 750mA IO1,2 = 750mA 7V < VIN1 < 14V 10V < VIN2 < 14V IO1,2 = 200mA 5mA < IO1 < 0.6A 5mA < IO2 < 0.6A IO1 = 10mA Output 2 Disabled K = VO1 See circuit description Ce = 100nF See circuit description I5 = 5mA V5 = 10V Tj = 0 to 125 C VO 106 KO = T VO VIN1 = 7V, VIN2 = 10V VIN1,2 = 16V (see Note) 2 0.8 0V < VDIS < 7V -100 145 2 o Min. 5 7.84 4.9 7.7 Typ. 5.1 8 Max. 5.2 8.16 5.3 8.3 1.4 50 80 100 160 2 Unit V V V V V mV mV mV mV mA V mV ms VO1,2LO IQ VO1RST VRTH tRD VRL IRH KO1,2 Load Regulation Quiescent Current Reset Thrseshold Voltage Reset Thrseshold Hysteresis Reset Pulse Delay Saturation Voltage in Reset Condition Leakage Current in Normal Condition at Pin 6 Output Voltage Thermal Drift K - 0.4 20 K0.25 50 25 K - 0.1 75 0.4 10 100 V µA ppm/ C o IO1,2SC VDISH VDISL IDIS Tjsd Short Circuit Output Current Disable Voltage High (out 2 active) Dis

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