Fairchild Semiconductor fdv302p free download

File name fdv302p.pdf

October 1997 FDV302P Digital FET, P-Channel General Description Features This P-Channel logic level enhancement mode field effect -25 V, -0.12 A continuous, -0.5 A Peak. transistor is produced using Fairchild's proprietary, high cell RDS(ON) = 13 @ VGS= -2.7 V density, DMOS technology. This very high density process is RDS(ON) = 10 @ VGS = -4.5 V. especially tailored to minimize on-state resistance. This device has been designed especially for low voltage Very low level gate drive requirements allowing direct applications as a replacement for digital transistors. Since operation in 3V circuits. VGS(th) < 1.5V. bias resistors are not required, this one P-channel FET can Gate-Source Zener for ESD ruggedness. replace several digital transistors with different bias resistors >6kV Human Body Model such as the DTCx and DCDx series. Compact industry standard SOT-23 surface mount package. Replace many PNP digital transistors (DTCx and DCDx) with one DMOS FET. SOT-23 SuperSOTTM-6 SuperSOTTM-8 SO-8 SOT-223 SOIC-16 Mark:302 D G S Absolute Maximum Ratings TA = 25oC unless otherwise noted Symbol Parameter FDV302P Units VDSS Drain-Source Voltage -25 V VGSS Gate-Source Voltage -8 V ID Drain Current - Continuous -0.12 A - Pulsed -0.5 PD Maximum Power Dissipation 0.35 W TJ,TSTG