Brother HL-600 free download

File name HL660TEC.PDF

LASER PRINTER SERVICE MANUAL MECHANICS & ELECTRONICS CHAPTER II 1. 1.1 THEORY OF OPERATION ELECTRONICS General Block Diagram Fig. 2.1 shows a general block diagram of this printer. Option RAM 1, 2, 4, 8MB Option I/F AT-2000 Control system I/O I/O Low-voltage power supply block Video control block Interface block I/O Option ROM Engine control block BR-2000 Operation block High-voltage power supply block (Operation panel) Drive block Laser scanner unit (Stepping motor) Paper tray unit Paper tray Drum unit Transfer block Manual feed Fixing unit Developing block Drum Cleaner block Charging block Eraser lamp Paper eject block Paper feed system Toner cartridge Image generation system Fig. 2.1 General Block Diagram II - 1 External device External device 1.2 Main PCB Block Diagram Fig. 2.2 shows a block diagram of the main PCB. ASIC µPD95137 CPU (MC68EC020) RESET CIRCUIT Data Control bus signal OSCILLATOR 49.08434MHz MEMORY CONTROL PROGRAM + FONT ROM 2MBytes CIRCUIT TIMER RAM 2MBytes VIDEO CONTROL CIRCUIT OPTION I/F (Apple Talk) PARALELL I/F P3 OPTION RAM 1, 2, 4, 8MBytes P4 ENGINE CONTROL CIRCUIT P2 CDCC CONNECTOR OPTION ROM 2MBytes P5 GENERAL I/O CONTROL CIRCUIT P1 TO DRIVER PCB EEPROM 4 Kbits Fig. 2.2 Main PCB Block Diagram II - 2 1.3 Main PCB 1.3.1 CPU The CPU is a Motorola MC68EC020FG25 which is driven with a clock frequency of 24.54217MHz. This clock frequency is made by the oscillator circuit of the ASIC. The CPU has a 24 bits address bus of A0-A23 and a 32 bits data bus of D0-D31. The total memory space of the CPU is 16 MBytes. Its package is a 160-pin QFP. The interrupts for the CPU is as follows. IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 : : : : : : : Timer DMA request for the video signals Timer Engine Option I/F Parallel I/F Timer, switches Fig. 2.3 CPU II - 3 1.3.2 ASIC The ASIC is a NEC µPD95137GD-5ML, which is consisted of the oscillator, the memory control circuit, the video control circuit, the parallel I/F, the engine control circuit and the general I/O control circuit. Its package is a 208-pin QFP. (1) Oscillator circuit This circuit generates the main clock of 49.08434 for the CPU by the internal oscillator. This clock is demultiplied into two and fed to the CPU. (2) Memory control circuit This block generates each control signal (RAS, CAS, OE, WE, MA) for the internal DRAM and the SIMM. Writing into the DRAM is performed by a early write method. The refresh is performed at the same timing of the ROM access or during nonaccess period for the CPU by the CBR (Cas Before Ras). (3) Video control circuit The video control block provides the FIFO and stores one laster data. Writing into the FIFO is performed by the DMA or CPU. (4) Parallel I/F The parallel I/F block performs the DMA data transmission after receiving data from the external device. (5) Engine control block This block is the I/O for connecting to the driver PCB, and controls the motor, solenoids, and sensors. (6) General I/O control